Thick Conductive Circuit Layout for Wire Bonding Pressure

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Solution Overview

Problem

Existing chip packages suffer from damage to internal circuits due to positive pressure during wire bonding, necessitating costly redesigns.

Innovation Solution

A chip package design with a conductive circuit thickness of 4.5-20 μm, comprising multiple dielectric and protective layers, enhances structural strength to withstand wire bonding pressures, allowing internal circuits to pass under bonding points without damage.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Reliability

If wire bonding is performed on existing chip packages, then electrical connection between chip package and electronic components is achieved, but internal circuit is damaged due to positive pressure during bonding

Engineering Contradiction:
Improveinternal circuit integrityVSAvoidpositive pressure damage
Core Design Contradiction:
ReliabilityVSObject-affected harmful factors

Solution Approach 1:

A conductive circuit layer with thickness of 4.5-20 μm is introduced as an intermediary structure between the bonding point and the internal circuit. This conductive circuit acts as a mediator that absorbs and distributes the positive pressure during wire bonding, preventing direct transmission of damaging forces to the internal circuit while maintaining electrical connectivity.

Inventive Principle:
Principle #24Intermediary (Mediator)

Solution Approach 2:

The thickness parameter of the conductive circuit is specifically optimized to range from 4.5-20 μm. This parameter change provides sufficient mechanical strength to withstand bonding pressure while maintaining electrical conductivity. The specific thickness range represents a critical balance point that resolves the contradiction between mechanical support and electrical function.

Inventive Principle:
Principle #35Parameter changes

2Reliability

If internal circuit is protected from positive pressure, then manufacturing cost increases due to circuit redesign

Engineering Contradiction:
Improveinternal circuit protectionVSAvoidmanufacturing cost
Core Design Contradiction:
ReliabilityVSEase of manufacture

Solution Approach 1:

The conductive circuit serves multiple functions simultaneously: it provides electrical connectivity, mechanical support during bonding, and pressure distribution. This multi-functionality eliminates the need for separate protective structures or circuit redesign, thereby protecting the internal circuit while maintaining manufacturing cost-effectiveness.

Inventive Principle:
Principle #6Universality (Multi-functionality)

3Strength

If conductive circuit thickness is increased to withstand bonding pressure, then structural strength improves but manufacturing complexity increases

Engineering Contradiction:
Improvestructural strengthVSAvoidconductive circuit structure
Core Design Contradiction:
StrengthVSDevice complexity

Solution Approach 1:

Rather than fundamentally changing the conductive circuit structure, the solution optimizes the thickness parameter within a specific range (4.5-20 μm). This parameter optimization achieves the required structural strength to withstand bonding pressure while avoiding excessive complexity. The defined thickness range represents an optimal balance between mechanical strength and manufacturing feasibility.

Inventive Principle:
Principle #35Parameter changes

Data Source

PatentUS12482771B2Chip package with higher bearing capacity in wire bonding
Publication Date: 2025.11.25 WALTON ADVANCED ENG INC
  • US12482771B2 patent drawing
  • US12482771B2 patent drawing
  • US12482771B2 patent drawing

AI summary

A chip package with higher bearing capacity in wire bonding is provided. The chip package includes at least one conductive circuit which is a structure with a thickness ranging from 4.5 μm to 20 μm. Thereby a structural strength of the conductive circuit is improved and able to stand a positive pressure generated in wire bonding or formation of a first bonding point. Thus at least one internal circuit of a chip will not be damaged by the positive pressure and allowed to pass through an area under the first bonding point or arrange under the first bonding point. A problem of increased cost at manufacturing end caused by the internal circuit redesign of the chip can be solved effectively. This is beneficial to cost reduction at manufacturing end.