Conductive Contact With Composite Spacer And Epitaxy
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Solution Overview
Problem
As semiconductor devices miniaturize, the dimensions of conductive contacts decrease, leading to increased contact resistances due to reduced surface area and aspect ratios of contact openings, which can result in voids and seams, causing open circuits and higher resistance.
Innovation Solution
A method involving the formation of conductive semiconductor layers over conductive regions and isolation elements, with a composite spacer and epitaxy process, followed by dielectric layer deposition and etching to create a conductive contact with a reduced aspect ratio and increased surface area, ensuring complete filling and reduced contact resistance.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If the dimensions of conductive contacts are reduced to increase device integration density, then device integration density is improved, but contact resistance increases
Solution Approach 1:
The patent transitions from forming contacts in a single vertical dimension to creating a three-dimensional contact structure that extends laterally along the sidewalls of the gate structure. The composite spacer forms on both sidewalls, and the conductive semiconductor layer is deposited to wrap around the gate structure, effectively adding a lateral dimension to the contact path and increasing the effective contact area without increasing the vertical contact opening size.
Solution Approach 2:
The conductive semiconductor layer is deposited to wrap around the gate structure, nesting the contact material within the spacer-defined region. The contact structure becomes nested within the composite spacer formation, creating a multi-layered configuration where the conductive layer is surrounded by the dielectric spacer material, effectively increasing the contact surface area within a confined space.
2Productivity
If the diameter of conductive contacts is reduced to increase integration density, then integration density is improved, but contact resistance increases due to reduced surface area
Solution Approach 1:
Instead of increasing the vertical contact opening area, the patent extends the contact surface area laterally by forming the composite spacer on both sidewalls of the gate structure. The conductive semiconductor layer is deposited to wrap around the gate, creating a lateral extension of the contact surface that increases the effective area without increasing the contact opening diameter.
Solution Approach 2:
The contact structure is segmented into multiple components: the vertical contact opening, the lateral extension along the sidewalls defined by the composite spacer, and the wrapped conductive semiconductor layer. This segmentation allows the contact surface area to be distributed across multiple surfaces (top surface and sidewalls) rather than concentrated in a single large opening.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This method effectively reduces contact resistance by forming a conductive contact with a larger surface area and controlled thermal budget, preventing voids and seams, and maintaining low resistance even as semiconductor devices shrink, thereby ensuring reliable electrical connections.
Implementation Method 1
performing an epitaxy process and forming a first conductive semiconductor layer over the pair of the first conductive regions and a second conductive semiconductor layer over the top surface of the isolation element and portions of the top surface of the pair of second conductive regions exposed by the second opening
Data Source
AI summary
A method for fabricating a conductive contact is provided, including: providing a semiconductor substrate with a gate structure and a pair of first conductive regions in a first region, and a pair of second conductive regions and an isolation element in the second region, and a first dielectric layer and a second dielectric layer thereon; forming a third dielectric layer and a fourth dielectric layer over the semiconductor substrate in the first region; forming a pattern mask layer with a first opening over the second dielectric layer in the second region; performing an etching process to the third and fourth dielectric layers in the first region and a portion of the first and second dielectric layers in the second region exposed by the first opening; removing the patterned mask layer; forming a first conductive semiconductor layer over the first conductive regions and a second conductive semiconductor layer over the isolation element and portions of the top surface of the second conductive regions; forming a fifth dielectric layer over the semiconductor substrate; forming a third opening in the fifth dielectric layer in the second region; and forming a conductive layer in the third opening.