Conductive Element Structure Using Metal Liner Mask for Via Etching
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Solution Overview
Problem
As semiconductor devices shrink, the process windows for photolithographic processing have become increasingly tight, making it challenging to maintain the ability to scale down devices while meeting design criteria.
Innovation Solution
A method involving the formation of a conductive element in an insulating layer through a process that includes forming a recess in a metal layer, selectively forming a metal liner on the recess' sidewall, and using the metal layer and liner as a mask to etch a via in the insulating layer, which allows for reduced critical dimensions without the need for spacer etch back or lithography on a spacer.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Manufacturing precision
If photolithographic processing is used to pattern semiconductor devices, then devices can be manufactured with standard processes, but the process windows become tighter as device size decreases, limiting further scaling
Solution Approach 1:
The patent applies preliminary action by forming metal spacers on the sidewalls of etched features before the actual via etching process. These spacers are deposited and patterned in advance to define the final critical dimensions, allowing the photolithography process to work with larger, more tolerant dimensions while achieving smaller final features through the spacer-defined etch process.
Solution Approach 2:
The patent transitions from two-dimensional photolithographic patterning to three-dimensional spacer-based patterning. By forming vertical metal spacers on sidewalls and using them as etch masks, the process adds a vertical dimension to the patterning approach, enabling critical dimension control that is decoupled from the lateral photolithographic resolution limits.
2Length of moving object
If device size is reduced to meet consumer demand for smaller devices, then device miniaturization is achieved, but the process windows for photolithographic processing become tighter
Solution Approach 1:
The metal spacers are formed in advance through deposition and patterning processes that occur before the critical via etch. This preliminary formation of dimensional references allows the final device features to be defined by the spacer thickness rather than direct photolithographic exposure, enabling smaller device dimensions with relaxed photolithographic process windows.
Solution Approach 2:
The metal spacers act as an intermediary element between the photolithographic patterning step and the final via formation. The spacers translate the larger photolithographic pattern into smaller final dimensions, serving as a mediating structure that decouples the photolithographic process parameters from the final critical dimensions.
3Productivity
If traditional photolithographic methods are used, then manufacturing processes remain simple, but the ability to scale down devices is limited by tightening process windows
Solution Approach 1:
By forming metal spacers as a preliminary step before via etching, the process enables advanced device scaling without requiring fundamental changes to the overall manufacturing flow. The spacer formation uses standard deposition and etching equipment, adding process steps but avoiding the need for new lithographic tools or techniques.
Solution Approach 2:
The metal spacers are formed through self-aligned processes where the spacer material is deposited conformally on the sidewalls of previously etched features. This self-alignment eliminates the need for additional lithographic alignment steps, allowing the process to scale to smaller dimensions without proportionally increasing complexity.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach enables the reduction of critical dimensions in features formed in the insulating layer, improving profile straightness and integrating easily into manufacturing processes, thus supporting the continued miniaturization of semiconductor devices.
Implementation Method 1
etching a via in the insulating layer using the metal layer and the metal liner as a mask
Implementation Method 2
selectively forming a metal liner on a sidewall of the recess
Data Source
AI summary
Conductive element structures and methods of manufacture thereof are disclosed. In some embodiments, a method of forming a conductive element in an insulating layer includes: forming a recess in a metal layer disposed over the insulating layer; selectively forming a metal liner on a sidewall of the recess; and etching a via in the insulating layer using the metal layer and the metal liner as a mask.