Conductive Feature Surface Recesses to Prevent BEOL Dishing
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Solution Overview
Problem
The dishing issue in conductive features used for back-end-of-line (BEOL) metallic interconnect structures and probe pads leads to a weakened wiring layer and increased yield losses during wafer acceptance testing and package stress testing, due to a thin central region caused by excessive polishing.
Innovation Solution
Forming a conductive feature with a plurality of recesses on its surface reduces the polishing area, mitigating the dishing issue by interrupting the polishing process and maintaining a thicker, more even surface.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Manufacturing precision
If polishing is performed to planarize the conductive feature surface, then surface flatness is improved, but the central region becomes thin leading to dishing
Solution Approach 1:
The patent divides the conductive feature surface into multiple segments by forming recesses at regular intervals. This segmentation prevents the polishing process from removing material uniformly across the entire surface, thereby preventing the thinning and dishing that would otherwise occur in the central region while still achieving adequate planarization.
2Manufacturing precision
If polishing area is increased to improve planarization coverage, then surface uniformity is improved, but dishing issue worsens
Solution Approach 1:
By segmenting the surface into multiple smaller polishing zones separated by recesses, the patent achieves uniform planarization across the conductive feature without the harmful effect of excessive material removal from the center. Each segment is polished independently, preventing the cumulative dishing effect.
Solution Approach 2:
The patent applies different treatments to different regions of the conductive feature surface. The recessed regions serve as spacers that prevent over-polishing, while the elevated regions receive the planarization treatment. This local differentiation allows surface uniformity to be achieved without compromising the central region thickness.
3Manufacturing precision
If polishing is performed to remove excess conductive material, then dimensional precision is improved, but mechanical strength decreases
Solution Approach 1:
The conductive feature is segmented into multiple raised regions separated by recesses. During polishing, the recesses act as barriers that prevent the polishing medium from accessing and removing material from the central regions. This allows dimensional precision to be achieved at the surfaces of the raised regions while preserving the thickness and strength of the central conductive material.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
The reduced polishing area helps in preventing mechanical weakness and excessive resistance in the conductive feature, enhancing the reliability and yield of the interconnect and pad structures.
Implementation Method 1
The dishing issue in conductive features used for back-end-of-line (BEOL) metallic interconnect structures and probe pads leads to a weakened wiring layer and increased yield losses during wafer acceptance testing and package stress testing, due to a thin central region caused by excessive polishing.
Data Source
AI summary
A method for forming a conductive feature includes following operations. A first insulating layer is formed over a substrate. The first insulating layer is patterned to form a first recess in the first insulating layer. The first recess is filled with a conductive material. A plurality of second recesses are formed in the conductive material. Each of the second recesses overlaps the first recess. A portion of the conductive material is removed to form a first conductive feature. A ratio of a sum of opening areas of the second recesses to an opening area of the first recess is less than 1%.