Conductive Feature Contact Resistance Reduction
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Solution Overview
Problem
The reduction in minimum feature size of semiconductor devices has led to increased contact resistance between conductive contacts and access transistors, deteriorating the operating speed of semiconductor devices due to reduced contact area.
Innovation Solution
The implementation of conductive features that extend into the substrate, with a lower portion having a funnel shape and increasing contact area, and a method of manufacturing involving the formation of sacrificial liners and contact holes to deposit conductive material, effectively reducing contact resistance.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If the minimum feature size is reduced to increase integration density, then the number of components integrated per area increases, but the contact resistance between conductive contacts and access transistors increases
Solution Approach 1:
The conductive feature is designed to extend vertically into the substrate beyond the surface level, transitioning from a two-dimensional contact to a three-dimensional structure. This vertical extension increases the contact area with the access transistor's impurity region, thereby reducing contact resistance while maintaining the reduced minimum feature size for high integration density.
Solution Approach 2:
The conductive feature is inserted into and nested within the impurity region of the access transistor, with the lower portion extending into the substrate. This nesting arrangement maximizes the overlap between the conductive feature and the impurity region, increasing the effective contact area and reducing contact resistance.
2Productivity
If the contact area between conductive features and access transistors is reduced due to smaller minimum feature size, then more components can be integrated, but the operating speed of the semiconductor device deteriorates
Solution Approach 1:
The conductive feature extends vertically into the substrate, utilizing the vertical dimension to compensate for the reduced horizontal contact area. This three-dimensional contact structure increases the total contact area with the impurity region, maintaining low contact resistance and thus preserving high operating speed despite the reduced minimum feature size.
Solution Approach 2:
The conductive feature's geometry is optimized by changing the critical dimension parameter along the vertical direction. The lower portion of the conductive feature has a smaller critical dimension that gradually increases toward the upper portion, creating a funnel shape that maximizes contact area with the impurity region while maintaining compatibility with the reduced minimum feature size.
Data Source
AI summary
The present disclosure provides a method for manufacturing a semiconductor device. The method includes providing a substrate comprising one or more isolation features defining active regions; forming at least one access transistor comprising a plurality of impurity regions, wherein the impurity regions are disposed in the substrate; depositing a dielectric layer to cover the access transistor; forming a first contact hole through the dielectric layer to expose the associated impurity region; forming a sacrificial liner in the first contact hole; removing a portion of the substrate exposed through the first contact hole and the sacrificial liner to form a second contact hole connected to the first contact hole; and forming a conductive feature in the first and second contact holes.