Conductive Feature Formation via Electroplating
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Solution Overview
Problem
The semiconductor industry faces challenges in increasing wafer throughput, reducing processing costs, improving gap-filling of dielectric material, and minimizing stress and warpage on wafers, particularly due to the complexity and number of processing steps required for forming interconnect structures in semiconductor devices.
Innovation Solution
The solution involves controlling the electroplating process to achieve different plating rates for conductive features of varying sizes, allowing larger features to act as vias while smaller features function as conductive lines within the same interconnect level, thereby reducing the number of patterning and passivation steps, and using a metal cap layer for enhanced testing and reduced warpage.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Manufacturing precision
If multiple conductive features (vias and lines) are formed using traditional separate patterning processes, then manufacturing precision can be maintained, but device complexity and processing time increase
Solution Approach 1:
The patent merges the formation of conductive vias and conductive lines into a single electroplating process. By using a photoresist layer with varying thickness (thinner for via regions, thicker for line regions) and controlling plating parameters, both feature types are created simultaneously in one process step, eliminating multiple patterning operations while maintaining manufacturing precision
Solution Approach 2:
The patent applies local quality by creating spatially varying photoresist thickness across the substrate. The photoresist is thinner in regions where vias are to be formed and thicker in regions where conductive lines are to be formed. This local variation in photoresist properties enables the electroplating process to differentiate between via and line formation zones, allowing precise control over where each feature type is created
2Manufacturing precision
If multiple separate patterning and passivation steps are used to form different conductive features, then manufacturing precision is maintained, but productivity decreases
Solution Approach 1:
The patent combines multiple sequential patterning and passivation steps into a single electroplating operation. By controlling photoresist thickness and plating parameters, the process simultaneously forms both vias and conductive lines in one wafer processing cycle, directly increasing wafer throughput while maintaining precision through the localized photoresist approach
Solution Approach 2:
The electroplating process operates continuously across the entire wafer surface, forming all conductive features (both vias and lines) in a single uninterrupted operation. This continuous action eliminates the need to stop, reposition, and reprocess between different feature types, maximizing productivity while maintaining precision through the pre-established photoresist thickness pattern
3Ease of manufacture
If conventional electroplating is used without parameter control, then process simplicity is maintained, but manufacturing precision deteriorates
Solution Approach 1:
The patent uses local quality by creating spatially varying photoresist thickness (thinner for via regions, thicker for line regions) to control where current density is highest during electroplating. This approach maintains process simplicity by using a single electroplating bath and standard equipment, while achieving precise height control through the localized photoresist geometry that naturally directs plating current to the desired features
Solution Approach 2:
The patent changes physical parameters of the electroplating process, specifically controlling photoresist thickness as a key parameter. By adjusting photoresist thickness locally across the wafer and controlling plating parameters such as current density and plating solution composition, the process achieves different plating rates in different regions, enabling precise height differentiation between vias and lines without complicating the overall manufacturing approach
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach increases wafer throughput, decreases processing costs, enhances dielectric material gap-filling, and minimizes stress and warpage by simplifying the formation of interconnect structures and improving testing efficiency.
Implementation Method 1
controlling the electroplating process to have different plating rates for different conductive feature sizes
Data Source
AI summary
Semiconductor devices and methods of forming the same are described. An embodiment is a device including a pad on a substrate. A passivation film is on the substrate and covering at least a portion of the pad. A first conductive feature is on the pad and has a planar top surface, with the first conductive feature having a first height as measured from the pad to the planar top surface of the first conductive feature. A second conductive feature is on the passivation film and has a non-planar top surface, with the second conductive feature having a second height as measured from the passivation film to the non-planar top surface of the second conductive feature.