Conductive Fill Process with Differential Nucleation Layer
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Solution Overview
Problem
As semiconductor technology nodes shrink beyond 20 nm, the processing window for forming integrated circuit components decreases, leading to challenges in fabricating components such as contacts, plugs, and interconnect structures due to increased complexity and issues like voids and seams in conductive material deposition.
Innovation Solution
A process involving the formation of an opening in a dielectric layer over a substrate, followed by a cleaning process that forms byproduct portions on the sidewalls, a nucleation layer deposition, and subsequent etching to create a differential thickness profile, allowing for a conductive material to be deposited with a higher rate in thicker areas, thus avoiding voids and seams by maintaining a consistent distance between sidewalls and ensuring uniform filling.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Manufacturing precision
If conventional deposition processes are used at smaller technology nodes (15 nm, 12 nm), then processing complexity increases, but voids and seams form in conductive material deposition
Solution Approach 1:
A nucleation layer is deposited conformally on the sidewalls before the main conductive material deposition. This preliminary action creates a foundation that promotes uniform deposition and prevents void formation during subsequent filling processes at smaller technology nodes.
Solution Approach 2:
The nucleation layer is applied selectively on the sidewalls of the opening rather than uniformly throughout. This local application ensures that the conductive material deposits preferentially where needed to prevent voids and seams, while maintaining control over the overall filling process.
2Productivity
If technology node is shrunk beyond 20 nm, then integration density improves, but processing window decreases
Solution Approach 1:
The process introduces a nucleation layer with specific material properties and thickness parameters that are optimized for smaller technology nodes. By changing the deposition parameters and introducing an intermediate layer, the processing window is effectively extended despite the reduced dimensions.
Solution Approach 2:
The deposition process is segmented into multiple stages: first depositing a nucleation layer conformally on sidewalls, then performing main conductive material deposition. This segmentation allows each stage to be optimized independently, maintaining precision at smaller nodes while achieving high integration density.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach reduces the occurrence of voids and seams in conductive structures at smaller technology nodes like 15 nm and 12 nm, enhancing device performance and yield by ensuring complete filling and preventing pinch-off effects during deposition.
Implementation Method 1
followed by a cleaning process that forms byproduct portions on the sidewalls
Implementation Method 2
a nucleation layer deposition
Implementation Method 3
subsequent etching to create a differential thickness profile
Data Source
AI summary
Methods of forming conductive structures and the conductive structures are disclosed. A method includes forming an opening in a dielectric layer over a substrate, performing a cleaning process on the dielectric layer with the opening, forming a nucleation layer in the opening, etching the nucleation layer in the opening, and forming a conductive material in the opening and on the nucleation layer after the etching. An upper portion of the opening is distal from the substrate, and a lower portion of the opening is proximate the substrate. After the etching, a thickness of an upper portion of the nucleation layer in the upper portion of the opening is less than a thickness of a lower portion of the nucleation layer in the lower portion of the opening.