Conductive Filling Pattern Layout for Self-Aligned Bit Line Contacts
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Solution Overview
Problem
In DRAM devices, misalignment during photo and etching processes can lead to undesirable relative positions between structures, affecting electrical connections and potentially causing shorts between the conductive filling pattern and the gate structure.
Innovation Solution
The semiconductor device incorporates a conductive filling pattern that is self-aligned to the gate structures, ensuring proper electrical connection between the bit line and active patterns without misalignment, by extending through the active pattern and pads, and having a specific width configuration to prevent shorts.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Manufacturing precision
If conventional photo and etching processes are used to form structures, then manufacturing complexity is reduced, but misalignment occurs between structures affecting electrical connections
Solution Approach 1:
The gate structure is formed first to serve as a reference for subsequent structure formation. The conductive filling pattern is then formed to contact the gate structure, ensuring proper alignment is established before other structures are added. This preliminary positioning prevents misalignment issues that would otherwise require complex alignment processes.
Solution Approach 2:
The gate structure acts as an intermediary reference element that mediates the alignment between the conductive filling pattern and the active pattern. By using the gate structure as a positioning reference, the patent avoids direct alignment between distant structures, thereby reducing alignment errors without increasing process complexity.
2Reliability
If conductive filling pattern is formed without self-alignment, then manufacturing process is simpler, but electrical shorts may occur between conductive filling pattern and gate structure
Solution Approach 1:
The conductive filling pattern is designed to automatically align with the gate structure through its geometric configuration and formation process. The pattern self-positions to contact the gate structure without requiring additional alignment steps or complex control mechanisms, thereby ensuring reliable electrical connection while maintaining manufacturing simplicity.
Solution Approach 2:
The gate structure is formed first as a reference, and the conductive filling pattern is subsequently formed to contact it. This preliminary positioning ensures that the conductive filling pattern automatically achieves proper alignment with the gate structure, preventing electrical shorts without requiring complex alignment processes.
3Manufacturing precision
If conductive filling pattern has uniform width, then manufacturing is easier, but it cannot prevent electrical shorts at critical positions
Solution Approach 1:
The conductive filling pattern employs asymmetric width configuration, being wider at certain positions and narrower at others. This asymmetric design allows the pattern to prevent electrical shorts at critical positions where wider spacing is needed, while maintaining narrower width in other areas to ensure proper contact. The asymmetry is achieved through standard photolithography processes without requiring complex fabrication steps.
Data Source
AI summary
A semiconductor device includes an active pattern on a substrate, a gate structure, a conductive filling pattern and a bit line structure on the conductive filling pattern. The gate structure extends through an upper portion of the active pattern, and has an upper surface higher than an upper surface of the active pattern. The conductive filling pattern includes a lower portion on the active pattern and an upper portion thereon. The lower portion contacts an upper sidewall of the gate structure, and the upper portion has a width greater than a width of the lower portion.