Conductive Gate Joint Word Line for 3D NAND Program Disturb
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Solution Overview
Problem
In 3D memory structures, program disturb occurs due to increased distance between memory cells at the interface between tiers, leading to delayed electron movement and hot electron injection, which affects memory cells in upper tiers, especially when the selected word line is in the upper tier and separated from the interface by one or more data word lines.
Innovation Solution
A conductive gate connects two non-data memory cells to the joint region between tiers, forming a joint word line in electrical contact with each memory cell, and a control circuit ramps down the joint word line voltage after a program verify phase, followed by a delay before ramping down non-joint word line voltages, to minimize delays and reduce program disturb.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Quantity of substance
If memory cells are arranged in multi-tier 3D stacked structure to increase storage capacity, then storage density is improved, but program disturb occurs due to increased distance between memory cells at the interface between tiers
Solution Approach 1:
A dummy memory cell is introduced as an intermediary element at the interface between first and second tiers of memory cells. This dummy cell acts as a mediator to prevent program disturb by absorbing excess charge and reducing the harmful electric field effects on adjacent memory cells, thereby resolving the reliability issue while maintaining the high-density 3D stacked structure.
Solution Approach 2:
The voltage applied to the dummy memory cell is dynamically changed during programming operations. By applying specific voltages to the dummy cell at different stages of the programming process, the electric field distribution is optimized to prevent electron injection into adjacent memory cells, thus eliminating program disturb while preserving the multi-tier architecture benefits.
2Ease of manufacture
If the distance between memory cells at the interface is increased due to tier stacking, then manufacturing ease is improved, but electron movement is delayed causing hot electron injection
Solution Approach 1:
The dummy memory cell serves as an intermediary that manages charge transport at the tier interface. It controls electron movement by providing a designated path for excess electrons, preventing delayed electron movement and hot electron injection while maintaining the manufacturing advantages of stacked tier architecture.
Solution Approach 2:
By dynamically adjusting the voltage parameters of the dummy memory cell during programming operations, the electric field strength is optimized to maintain appropriate electron movement speed. This prevents electron accumulation and hot electron injection while preserving the structural benefits of increased tier spacing for manufacturing.
3Reliability
If a conductive gate connects non-data memory cells to the joint region to form a joint word line, then program disturb is reduced, but device complexity increases
Solution Approach 1:
The conductive gate connecting non-data memory cells to the joint region is merged with the existing word line structure to form a joint word line. This integration approach reduces program disturb by providing unified control over the interface region while minimizing the increase in device complexity through structural consolidation rather than adding completely separate components.
Solution Approach 2:
The joint word line structure serves multiple functions: it controls the dummy memory cell, manages charge at the tier interface, and prevents program disturb on adjacent memory cells. This multi-functionality reduces the need for separate control mechanisms, thereby limiting the increase in device complexity while achieving improved reliability.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This solution effectively reduces program disturb by efficiently clearing residual electrons from the joint region, improving channel conductivity and reliability in multi-tier 3D NAND memory devices, particularly in high aspect ratio BiCS with 2-tier architectures.
Implementation Method 1
The conductive gate forms a joint word line in electrical contact with a gate of each of the first and second non-data memory cells
Implementation Method 2
program disturb occurs due to injection of electrons at a joint region between tiers of memory cells
Data Source
AI summary
Techniques for reducing program disturb of memory cells which are formed in a NAND string extending in a lower tier and an upper tier of a stack, the lower tier including a first plurality of memory cells and the upper tier including a second plurality of memory cells, wherein each memory cell of the first and second pluralities of memory cells is connected to a respective word line. The NAND string includes a joint region formed of a dielectric material and disposed between the lower tier and the upper tier of the stack; a first non-data memory cell adjacent to and below the joint region; a second non-data memory cell adjacent to and above the joint region; and a conductive gate connected to the first non-data memory cell and the second non-data memory cell.