Conductive Grid Packaging Substrate for IC Warpage Control

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Solution Overview

Problem

The thickness of integrated circuit (IC) packages is limited by the packaging substrate, which undergoes warpage due to thermal expansion mismatch between metallic conductive traces and dielectric materials, leading to rigidity issues that cannot be adequately addressed by reducing substrate thickness.

Innovation Solution

A packaging substrate with an electrically conductive grid formed on a dielectric layer, replacing traditional power or ground planes, which reduces material usage and stress, allowing for thinner substrates without warpage by distributing thermal expansion mismatch stresses more effectively.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Length of moving object

If the packaging substrate thickness is reduced to minimize IC package size, then the IC package thickness is reduced, but the packaging substrate undergoes unacceptable warpage during operation due to thermal expansion mismatch

Engineering Contradiction:
ImproveIC package thicknessVSAvoidpackaging substrate planarity
Core Design Contradiction:
Length of moving objectVSStability of the object's composition

Solution Approach 1:

The continuous power plane or ground plane is segmented into a grid pattern of conductive portions separated by void regions. This segmentation reduces the total amount of metallic material in the substrate, thereby reducing thermal expansion stress while maintaining electrical connectivity and mechanical stability even at reduced substrate thickness

Inventive Principle:
Principle #1Segmentation

Solution Approach 2:

The packaging substrate incorporates a grid structure with void regions that are substantially free of electrically conductive material. This porous-like structure reduces the density of metallic material, decreasing thermal expansion mismatch stress and allowing thinner substrates to maintain planarity during operation

Inventive Principle:
Principle #31Porous materials

2Reliability

If traditional power planes or ground planes are used in the packaging substrate, then electrical connectivity is ensured, but thermal expansion mismatch causes warpage and rigidity issues

Engineering Contradiction:
Improveelectrical connectivityVSAvoidsubstrate planarity
Core Design Contradiction:
ReliabilityVSStability of the object's composition

Solution Approach 1:

The power plane or ground plane is divided into discrete conductive portions arranged in a grid pattern. These segmented conductive portions remain electrically connected through vias and trace interconnects, maintaining electrical reliability while reducing continuous metallic material that causes thermal expansion warpage

Inventive Principle:
Principle #1Segmentation

Solution Approach 2:

The structure of the power/ground plane is changed from a continuous solid layer to a grid pattern with controlled void regions. This parameter change in the geometric configuration reduces the effective thermal mass and expansion stress while preserving electrical functionality through strategic placement of conductive elements

Inventive Principle:
Principle #35Parameter changes

Applied Scientific Principles

This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.

Function Achieved in This Case

The electrically conductive grid configuration maintains planarity and reduces thermally induced stress, enabling thinner packaging substrates with increased flexibility and reduced rigidity-related issues, thus facilitating smaller and lighter mobile computing devices.

Implementation Method 1

Due to of this mismatch in CTE, when an IC package reaches operational temperature, warpage of the IC package can occur unless the packaging substrate is sufficiently rigid

Methodology Applied
Scientific EffectThermal expansion mismatch: Thermal Expansion

Data Source

PatentUS9831189B2Integrated circuit package with a conductive grid formed in a packaging substrate
Publication Date: 2017.11.28 NVIDIA CORP
  • US9831189B2 patent drawing
  • US9831189B2 patent drawing
  • US9831189B2 patent drawing

AI summary

An integrated circuit package includes a packaging substrate, which has an electrically conductive grid formed on a dielectric layer, and an integrated circuit die electrically coupled to the electrically conductive grid at one or more locations. In this embodiment, the electrically conductive grid includes a plurality of electrically conductive portions, wherein each portion is electrically coupled to at least one other portion, and a plurality of void regions that are electrically non-contiguous and substantially free of electrically conductive material. One advantage of the integrated circuit package is that a packaging substrate that is reduced in thickness, and therefore rigidity, can still maintain planarity during operation. The electrically conductive grid formed on a dielectric layer in the packaging substrate can replace a power plane or a ground plane in the packaging substrate, thereby reducing stressed produced as a result of thermal expansion mismatch between materials in the packaging substrate.