Conductive Hard Mask for Oxide Semiconductor Edge Control
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Solution Overview
Problem
Miniaturization of transistors leads to decreased yield due to unevenness in oxide semiconductor film side surfaces, affecting electrical characteristics and reliability.
Innovation Solution
The use of a hard mask with conductivity to microfabricate oxide semiconductor films, reducing line edge roughness and allowing the hard mask to serve as part of the source or drain electrodes, along with a specific multi-layer oxide film structure to improve channel formation and reduce oxygen vacancies.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Length of moving object
If the oxide semiconductor film is microfabricated to have an island shape, then the transistor size is reduced for high-speed operation and low power consumption, but unevenness is generated at the side surface of the oxide semiconductor film, causing increased variations in shape and adverse effects on electrical characteristics and reliability
Solution Approach 1:
A hard mask is introduced as an intermediary layer between the resist mask and the oxide semiconductor film during microfabrication. This hard mask serves as a protective intermediary that prevents direct exposure and damage to the oxide semiconductor film side surfaces, thereby reducing line edge roughness and side surface unevenness while enabling miniaturization.
Solution Approach 2:
The hard mask is formed on the oxide semiconductor film before the etching process. This preliminary formation of the hard mask layer protects the oxide semiconductor film from direct etching damage, preventing side surface unevenness from occurring in the first place during the miniaturization process.
2Productivity
If the transistor is miniaturized, then high integration and low power consumption are achieved, but the yield of transistors in the manufacturing process is decreased due to increased variations in shape
Solution Approach 1:
The hard mask acts as a protective intermediary that ensures uniform and precise patterning of the oxide semiconductor film during miniaturization. By reducing line edge roughness and side surface unevenness, it maintains consistent transistor geometry across the wafer, thereby improving yield while enabling high integration.
Solution Approach 2:
The introduction of the hard mask changes the etching parameters and process conditions. This parameter change enables more precise control over the etching depth and side surface profile, maintaining manufacturing precision even at reduced transistor dimensions and ensuring high yield.
3Manufacturing precision
If a hard mask is used to reduce line edge roughness, then manufacturing precision is improved, but the device structure becomes more complex
Solution Approach 1:
The hard mask is designed to serve multiple functions: it acts as a protective layer during etching, defines the pattern geometry, and can be integrated with subsequent electrode formation processes. This multi-functionality justifies the additional layer by providing several benefits within a single structural element.
Solution Approach 2:
The hard mask formation process is merged with the existing photolithography and etching工艺流程. By combining the protective function, patterning function, and electrode integration function into a unified process sequence, the additional complexity is minimized while achieving the desired manufacturing precision.
Data Source
AI summary
When an oxide semiconductor film is microfabricated, with the use of a hard mask, unevenness of a side surface of the oxide semiconductor film can be suppressed. Specifically, a semiconductor device comprises an oxide semiconductor film over an insulating surface; a first hard mask and a second hard mask over the oxide semiconductor film; a source electrode over the oxide semiconductor film and the first hard mask; a drain electrode over the oxide semiconductor film and the second hard mask; a gate insulating film over the source electrode and the drain electrode; and a gate electrode overlapping with the gate insulating film and the oxide semiconductor film, and the first and second hard masks have conductivity.