Conductive Island Formation for DRAM Landing Pad Isolation

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Solution Overview

Problem

The semiconductor industry faces challenges in forming landing pads for DRAM cells with increasing integrated circuit density, as the process becomes more complex and difficult to separate landing pads in dense arrays, leading to potential shorting issues between conductive elements.

Innovation Solution

A method involving a substrate with a conductive layer, patterned to form conductive patterns, covered by a cap layer and a patterned hard mask, where the conductive patterns are etched to create conductive islands separated by gaps and the cap layer, mitigating shorting by forming a grid-like structure.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Quantity of substance

If integrated circuit density is increased by reducing dimensions and spacing between components, then packing density of DRAM chip is improved, but manufacturing complexity and difficulty increase

Engineering Contradiction:
Improvepacking densityVSAvoidmanufacturing complexity
Core Design Contradiction:
Quantity of substanceVSDevice complexity

Solution Approach 1:

The conductive layer is divided into multiple isolated conductive islands separated by gaps and the cap layer, rather than forming continuous landing pads. This segmentation approach allows each conductive island to be independently formed and controlled, simplifying the manufacturing process while maintaining high packing density.

Inventive Principle:
Principle #1Segmentation

Solution Approach 2:

The cap layer is introduced as an intermediary material between the conductive patterns and the etching process. This cap layer enables selective etching to form isolated conductive islands, providing a straightforward manufacturing approach that avoids the complexity of forming separate landing pads in dense arrays.

Inventive Principle:
Principle #24Intermediary (Mediator)

2Area of stationary object

If landing pads are formed in dense arrays to increase packing density, then area occupied on chip is reduced, but process complexity increases and shorting issues arise

Engineering Contradiction:
Improvearea occupiedVSAvoidprocess complexity
Core Design Contradiction:
Area of stationary objectVSDevice complexity

Solution Approach 1:

Instead of forming continuous landing pads in dense arrays, the conductive layer is segmented into isolated conductive islands. These islands are separated by gaps and the cap layer, which prevents shorting while occupying minimal area. This segmentation simplifies the formation process compared to traditional landing pad fabrication in dense configurations.

Inventive Principle:
Principle #1Segmentation

Solution Approach 2:

The cap layer is conformally deposited over the conductive patterns and then selectively removed in gap regions through etching. This extraction of the cap layer in specific areas creates isolated conductive islands, providing a simple and effective approach to prevent shorting without requiring complex multi-step landing pad formation processes.

Inventive Principle:
Principle #2Taking out (Extraction)

3Quantity of substance

If conductive elements are placed closer together to increase density, then packing density is improved, but risk of shorting between elements increases

Engineering Contradiction:
Improvepacking densityVSAvoidshorting prevention
Core Design Contradiction:
Quantity of substanceVSReliability

Solution Approach 1:

The cap layer serves as an intermediary insulating barrier between adjacent conductive islands. By conformally depositing the cap layer over the conductive patterns and selectively etching it in gap regions, the remaining cap layer portions provide reliable electrical isolation between closely spaced conductive elements, preventing shorting while maintaining high packing density.

Inventive Principle:
Principle #24Intermediary (Mediator)

Solution Approach 2:

Instead of relying solely on horizontal gaps to prevent shorting, the solution utilizes the vertical dimension by forming a cap layer that extends over the conductive patterns. This three-dimensional approach provides additional insulation pathways and ensures reliable separation between conductive elements even when horizontally spaced very closely.

Inventive Principle:
Principle #17Another dimension (Dimensionality change)

Data Source

PatentUS10763262B2Method of preparing semiconductor structure
Publication Date: 2020.09.01 NAN YA TECH
  • US10763262B2 patent drawing
  • US10763262B2 patent drawing
  • US10763262B2 patent drawing

AI summary

The present disclosure provides a method for preparing a semiconductor structure. The method includes the following steps. A substrate including a conductive layer formed thereon is provided. The conductive layer is patterned to form a plurality of conductive patterns extending along a first direction. A cap layer is conformally formed to cover the plurality of conductive patterns. A patterned hard mask is formed over the cap layer. The plurality of conductive patterns are etched through the patterned hard mask to form a plurality of conductive islands. In some embodiments, the plurality of conductive islands are separated from each other by a plurality of first gaps along the first direction. In some embodiments, the plurality of conductive islands are separated from each other by the cap layer and a plurality of second gaps along a second direction that is different from the first direction.