Conductive Layer in Pleated Sidewall Encapsulant Opening
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Solution Overview
Problem
Wafer level semiconductor packages without a stress buffer exhibit poor reliability compared to those with a stress buffer, due to increased stress from temperature differences and thermal expansion coefficients between the conductive interconnection structures and the encapsulant.
Innovation Solution
A semiconductor package design featuring a conductive layer with high adhesion between the encapsulant and conductive interconnection structures, formed on the sidewalls of encapsulant openings, which reduces stress by increasing coupling forces and improving board level reliability.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Ease of manufacture
If wafer level packages are packaged without a stress buffer, then packaging costs are reduced, but reliability deteriorates due to increased stress from temperature differences and thermal expansion coefficients
Solution Approach 1:
A conductive layer is introduced as an intermediary between the encapsulant and the conductive interconnection structures. This conductive layer serves as a stress buffer that mediates the thermal expansion differences between the encapsulant and interconnection structures, preventing direct stress transmission while maintaining electrical conductivity.
Solution Approach 2:
The thermal expansion coefficient parameter is modified by introducing the conductive layer with different thermal expansion properties between the encapsulant and interconnection structures. This parameter change allows the system to accommodate thermal stress through controlled expansion differences rather than direct stress transmission.
2Reliability
If a conductive layer is added on the sidewalls of encapsulant openings, then stress is reduced and reliability is improved, but device complexity increases
Solution Approach 1:
The conductive layer is applied locally only on the sidewalls of the encapsulant openings rather than throughout the entire package structure. This localized application provides stress relief at the critical interface between encapsulant and interconnection structures without adding complexity to the entire device.
Solution Approach 2:
The package structure becomes a composite system with the conductive layer forming a composite interface between the encapsulant and interconnection structures. This composite material approach combines the benefits of stress buffering with electrical conductivity, achieving reliability improvement without significant complexity increase.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
The solution effectively reduces stress on conductive interconnection structures, enhancing the reliability of wafer level semiconductor packages by mitigating the effects of temperature and thermal expansion coefficient differences between the interconnection structures and the encapsulant.
Implementation Method 1
A semiconductor package design featuring a conductive layer with high adhesion between the encapsulant and conductive interconnection structures
Implementation Method 2
reduces stress by increasing coupling forces and improving board level reliability... mitigating the effects of temperature and thermal expansion coefficient differences
Data Source
AI summary
A semiconductor package, and a method of manufacturing thereof, comprising a contact in a plated sidewall encapsulant opening, substantially as shown in and/or described in connection with at least one of the figures, as set forth more completely in the claims.