Conductive Line Cut Patterning for Reduced Line-End Spacing
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Solution Overview
Problem
The semiconductor industry faces challenges in reducing line end spacing below the limits of traditional optical masks and photolithography equipment, hindering further integration density improvements.
Innovation Solution
A method for forming conductive lines with dielectric cut features, involving multiple hard mask layers and precise patterning techniques, including EUV photolithography, to achieve narrower line-end spacing.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Manufacturing precision
If traditional optical masks and photolithography equipment are used, then manufacturing process is simple and well-established, but line end spacing cannot be reduced below a certain limit
Solution Approach 1:
The patterning process is divided into multiple stages: first forming initial lines with photolithography, then using self-aligned multiple patterning (SAMP) to further subdivide and refine the pattern. This segmentation allows achieving sub-lithographic line end spacing by breaking down the complex patterning task into manageable steps, each with its own mask and etch process.
Solution Approach 2:
Mandrel structures are formed in advance before the final pattern transfer. These preliminary mandrels serve as templates that guide subsequent self-aligned etching processes, enabling precise line end spacing control. The mandrels are strategically positioned and dimensioned to pre-determine the final pattern geometry, reducing the need for complex real-time adjustments.
2Manufacturing precision
If minimum feature size is reduced to increase integration density, then more components can be integrated into a given chip area, but manufacturing approaches theoretical limits of photolithography equipment
Solution Approach 1:
Self-aligned spacer structures are introduced as intermediary elements between the lithographically defined mandrels and the final pattern. These spacers act as mediators that transfer and refine the pattern with higher precision, enabling feature sizes below the direct photolithography limit while maintaining manufacturing reliability through self-aligned processes that reduce alignment errors.
Solution Approach 2:
The patent employs multiple parameter changes including varying etch selectivities between different layers, adjusting spacer thicknesses, and modifying mandrel dimensions to optimize the self-aligned multiple patterning process. By carefully controlling these parameters, the process achieves reliable sub-lithographic patterning that overcomes the theoretical limits of conventional photolithography.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
Enables the formation of conductive lines with reduced line-end spacing, facilitating advanced semiconductor device manufacturing beyond the limitations of conventional photolithography.
Implementation Method 1
patterning the second hard mask layer using extreme ultraviolet (EUV) patterning technology to form a plurality of mask strips over the first hard mask layer
Data Source
AI summary
Embodiments of the present disclosure provide methods for forming conductive lines with dielectric cut features. Particularly, embodiments of present disclosure provide a method for forming conductive line pattern using two patterning processes. A line pattern is formed in the first patterning process. A cut pattern is formed over the line pattern in the second patterning process. The cut pattern is formed by forming cut openings with a width smaller than the line width of the line pattern and then filling the cut opening with a mask material.