Conductive Liner Interconnects for Lower BEOL Contact Resistance
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Solution Overview
Problem
Current integrated circuit fabrication processes face challenges in scaling to smaller feature sizes due to variability in lithographic processes, leading to increased contact resistance and alignment issues in back-end-of-line (BEOL) structures, which limits the ability to extend technology nodes beyond the 15 nanometer range.
Innovation Solution
The implementation of a conductive liner beneath a copper structure in BEOL interconnects to reduce contact resistance, combined with the use of differentiated metal layers and pitch quartering approaches for precise patterning, enabling finer features and improved scalability.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Manufacturing precision
If conventional fabrication processes are used for scaling, then manufacturing simplicity is maintained, but contact resistance increases and manufacturing precision deteriorates at 15 nanometer node and below
Solution Approach 1:
The conductive line structure is segmented into multiple functional layers: a barrier layer (e.g., tantalum nitride) and a conductive liner layer (e.g., cobalt or tungsten). This segmentation allows each layer to perform its specialized function - the barrier layer prevents diffusion while the liner layer provides low contact resistance, thereby improving manufacturing precision without excessive complexity
Solution Approach 2:
The invention uses composite material structures combining different materials with complementary properties. The barrier layer (tantalum nitride) combined with conductive liner (cobalt/tungsten) creates a composite structure that simultaneously achieves low contact resistance and process compatibility, resolving the contradiction between precision and complexity
2Productivity
If feature size is reduced to increase device density, then productivity is improved, but lithographic variability increases leading to alignment issues
Solution Approach 1:
The invention addresses lithographic limitations by moving to another dimension - using atomic layer deposition (ALD) to form conformal barrier and liner layers that wrap around via structures. This dimensional transition from planar lithography to conformal thin-film deposition enables precise control at scales below lithographic resolution, maintaining alignment precision while achieving higher device density
Solution Approach 2:
The invention changes material parameters by selecting specific materials with appropriate properties for each layer. The barrier layer uses materials like tantalum nitride with controlled thickness (2-5 nm), and the conductive liner uses cobalt or tungsten, optimizing electrical and structural parameters to maintain precision at reduced feature sizes
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach results in a 20-25% reduction in contact resistance and allows for increased current density, enabling continued scaling of metal layers beyond the resolution limits of existing lithography, while maintaining low resistivity and reducing electromigration issues.
Implementation Method 1
The conductive liner is directly on the conductive via and under the conductive barrier, where the conductive liner is to reduce contact resistance
Data Source
Figure 1A~1B
Figure 1C
Figure 2A
AI summary
Embodiments of the disclosure are in the field of integrated circuit structure fabrication. In an example, an integrated circuit structure includes a conductive via in a first dielectric layer. The integrated circuit structure also includes a conductive line in a second dielectric layer, the conductive including a conductive liner having a conductive barrier therein, the conductive barrier having a conductive fill therein, wherein the conductive liner is directly on the conductive via.