Conductive Metal Liner for Low-Resistance IC Lines and Vias
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Solution Overview
Problem
Current integrated circuit fabrication processes face challenges in scaling to sub-15 nanometer nodes due to variability in conventional methods, leading to limitations in reducing contact resistance between conductive lines and vias, and achieving optimal performance with both narrow and wide metal lines.
Innovation Solution
The introduction of a conductive liner beneath copper structures and the use of hybrid metal layers with different compositions for narrower and wider lines, along with advanced patterning techniques like pitch quartering and halving, to reduce contact resistance and enhance scalability.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Manufacturing precision
If conventional fabrication processes are used for scaling, then manufacturing simplicity is maintained, but manufacturing precision deteriorates at sub-15 nanometer nodes
Solution Approach 1:
The fabrication process is divided into multiple patterning steps (pitch quartering, pitch halving) to achieve sub-15nm precision. Each step creates intermediate patterns that are combined to form the final high-resolution structure, breaking down the complex task of creating sub-15nm features into manageable sequential operations
Solution Approach 2:
Mandrel structures are formed in advance before the final conductive line patterning. These preliminary mandrels serve as templates for subsequent spacer formation and pattern transfer, enabling precise feature definition at sub-15nm nodes through a sequence of preparatory steps
2Reliability
If copper structures are used without conductive liner, then ease of manufacture is maintained, but contact resistance increases
Solution Approach 1:
A conductive liner is introduced as an intermediary layer between the copper fill and the surrounding dielectric or barrier materials. This liner layer improves contact resistance and electrical performance while maintaining the manufacturing simplicity of copper electroplating, as the liner can be deposited using standard PVD or ALD processes integrated into existing fabrication flows
3Reliability
If uniform metal line composition is used, then ease of manufacture is maintained, but performance optimization for different line widths is limited
Solution Approach 1:
Different metal compositions are used for different line width regions. Narrower lines use one metal composition optimized for their specific electrical and electromigration characteristics, while wider lines use a different composition. This local differentiation allows performance optimization for each line type while using standard fabrication processes to create the varied structure
Data Source
AI summary
Embodiments of the disclosure are in the field of integrated circuit structure fabrication. In an example, an integrated circuit structure includes a conductive via in a first dielectric layer. The integrated circuit structure also includes a conductive line in a second dielectric layer, the conductive including a conductive liner having a conductive barrier therein, the conductive barrier having a conductive fill therein, wherein the conductive liner is directly on the conductive via.