Conductive Line Patterning With Dielectric Cuts for Tighter Line Ends

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Solution Overview

Problem

The semiconductor industry faces challenges in reducing line end spacing below the limits of traditional optical masks and photolithography equipment, hindering further integration density improvements in semiconductor devices.

Innovation Solution

A method for forming conductive lines with dielectric cut features involves multiple patterning processes using hard mask layers and photoresist structures, including EUV lithography, to create precise line and cut patterns, allowing for reduced line-end spacing through sequential pattern transfer and etching.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Manufacturing precision

If traditional optical masks and photolithography equipment are used, then manufacturing process is simple, but line end spacing cannot be reduced below certain limit

Engineering Contradiction:
Improveline end spacingVSAvoidpatterning process complexity
Core Design Contradiction:
Manufacturing precisionVSDevice complexity

Solution Approach 1:

The patterning process is divided into multiple sequential steps: first forming initial patterns with photolithography, then using hard mask layers and additional etching steps to create final patterns with reduced line end spacing. This segmentation allows achieving precision beyond single-step photolithography limits.

Inventive Principle:
Principle #1Segmentation

Solution Approach 2:

Hard mask layers are deposited and patterned in advance before the final etching step. This preliminary action establishes a precise template that guides subsequent etching processes, enabling accurate pattern transfer with reduced line end spacing that cannot be achieved by photolithography alone.

Inventive Principle:
Principle #10Preliminary action

2Quantity of substance

If multiple patterning processes are used to reduce line end spacing, then integration density improves, but manufacturing process complexity increases

Engineering Contradiction:
Improveintegration densityVSAvoidpatterning process complexity
Core Design Contradiction:
Quantity of substanceVSDevice complexity

Solution Approach 1:

The manufacturing process is segmented into distinct stages: photolithography patterning, hard mask deposition, hard mask patterning, and final etching. Each stage contributes to the overall integration density improvement while maintaining manageable complexity through systematic division of tasks.

Inventive Principle:
Principle #1Segmentation

Solution Approach 2:

Hard mask layers serve as intermediary structures between photolithography patterns and final conductive line patterns. These intermediate hard masks enable precise pattern transfer and facilitate the reduction of line end spacing, acting as a bridge that allows integration density improvement without overwhelming process complexity.

Inventive Principle:
Principle #24Intermediary (Mediator)

Applied Scientific Principles

This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.

Function Achieved in This Case

This method enables the formation of conductive lines with reduced line-end spacing, overcoming the limitations of traditional photolithography and enhancing integration density in semiconductor devices.

Implementation Method 1

including EUV lithography, to create precise line and cut patterns

Methodology Applied
Scientific EffectEUV lithography: Photopolymerisation

Implementation Method 2

patterning the second hard mask layer to form a plurality of mask strips over the first hard mask layer

Methodology Applied
Scientific EffectEtching:

Data Source

PatentUS12412778B2Method for reducing line end spacing and semiconductor devices manufactured thereof
Publication Date: 2025.09.09 TAIWAN SEMICONDUCTOR MANUFACTURING CO LTD
  • US12412778B2 patent drawing
  • US12412778B2 patent drawing
  • US12412778B2 patent drawing

AI summary

Embodiments of the present disclosure provide methods for forming conductive lines with dielectric cut features. Particularly, embodiments of present disclosure provide a method for forming conductive line pattern using two patterning processes. A line pattern is formed in the first patterning process. A cut pattern is formed over the line pattern in the second patterning process. The cut pattern is formed by forming cut openings with a width smaller than the line width of the line pattern and then filling the cut opening with a mask material.