Conductive Lines for Multichip Module Interconnects
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Solution Overview
Problem
In multichip packages (MCPs), the increased density and reduced size of semiconductor chips lead to issues such as wire sweeping and broken wire bonds due to longer wire lengths and closer terminal spacing, limiting the number of adjacent wire bond connections and increasing manufacturing defects.
Innovation Solution
The method involves forming conductive lines on a semiconductor substrate that are electrically isolated from the circuits, allowing for the separation of die areas to form individual semiconductor chips with optimized terminal connections, and using conductive lines or through-silicon vias to connect chips, reducing wire bond length and improving connection efficiency.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If wire bonds are used to connect terminals on upper chip to substrate pads, then electrical connections are established, but wire bonds become longer and form greater angles, causing wire sweeping and short circuits
Solution Approach 1:
The patent introduces an intermediary substrate layer with conductive pads positioned between the upper chip terminals and the lower chip terminals. This intermediary structure serves as a mediator that receives wire bonds from the upper chip and provides wire bonds to the lower chip, thereby breaking the direct long wire bond path and preventing wire sweeping while maintaining electrical connectivity
Solution Approach 2:
The patent utilizes the vertical dimension by stacking chips in multiple layers with an intermediary substrate in between. Instead of having wire bonds traverse horizontally across a large distance, the connection path is distributed across multiple vertical layers, reducing the wire bond length and angle in each segment and preventing wire sweeping
2Quantity of substance
If terminals are spaced closer together to increase density, then more connections can be made, but the number of adjacent wire bond connections is limited
Solution Approach 1:
The patent segments the connection function across multiple substrate layers, where each layer handles a portion of the wire bond connections. This segmentation allows terminals to be spaced closer together on each individual chip while the intermediary substrates distribute the connection load, effectively increasing the total number of adjacent wire bond connections beyond what a single substrate could support
3Reliability
If wire bond length is reduced to prevent sweeping, then connection reliability improves, but the ability to connect distant terminals is limited
Solution Approach 1:
The intermediary substrate acts as a mediator that provides connection flexibility locally while maintaining short wire bond lengths. Each intermediary substrate can be configured with conductive pads in various patterns to accommodate different terminal arrangements, providing adaptability without requiring long wire bonds that would compromise reliability
Data Source
AI summary
Conductive lines are formed on a wafer containing multiple circuits. The conductive lines are isolated from the circuits formed within the wafer. Chips are mounted on the wafer and have their chip pads connected to the conductive lines of the wafer. The wafer may then be protected with a packaging resin and singulated.