Conductive Mask Etch Selectivity for Via Alignment in Semiconductor Devices
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Solution Overview
Problem
As semiconductor technologies advance, accurate alignment and overlay of vias and metal lines become increasingly problematic due to their decreasing sizes, leading to potential misalignment and undesirable over-etching in conventional fabrication methods.
Innovation Solution
A semiconductor device and method involving a conductive mask with a lower etch rate than the second conductive pattern, which is used to protect underlying metal and ensure precise alignment and formation of vias and metal lines through a damascene operation, including the use of a tapered profile for via holes to mitigate the 'necking effect' during copper filling.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If conventional damascene fabrication methods are used with decreasing via and metal line sizes, then manufacturing scalability is improved, but alignment precision deteriorates leading to misalignment between vias and metal lines
Solution Approach 1:
A conductive mask layer is introduced as an intermediary between the etch process and the underlying metal layers. This mask layer with controlled etch selectivity acts as a protective mediator that prevents over-etching and ensures precise via formation aligned with metal lines, solving the alignment precision problem while maintaining manufacturing scalability
2Device complexity
If conventional etching processes are used without protective masks, then process simplicity is improved, but reliability deteriorates due to over-etching of underlying metal
Solution Approach 1:
The conductive mask layer is formed in advance before the via etching process. This preliminary action creates a protective barrier that prevents over-etching of the underlying metal during subsequent processing steps, thereby improving device reliability without significantly complicating the overall fabrication process
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
The solution effectively addresses alignment issues and reduces over-etching by using a conductive mask with a lower etch rate, ensuring accurate and precise formation of vias and metal lines, thereby improving the reliability of semiconductor devices.
Implementation Method 1
The conductive mask has a lower etch rate to a predetermined etchant than the second conductive pattern
Implementation Method 2
a tapered profile for via holes to mitigate the 'necking effect' during copper filling
Data Source
AI summary
The present disclosure provides a semiconductor device. The semiconductor device includes a substrate having a first conductive pattern and a conductive mask disposed over the first conductive pattern. The semiconductor device further includes a second conductive pattern disposed over the conductive mask, and electrically connecting with the first conductive pattern through the conductive mask. The conductive mask has a lower etch rate to a predetermined etchant than the second conductive pattern. A method for forming the semiconductor device is also provided.