3D Memory Conductive Pad Tier for Bond Pad Miniaturization
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Solution Overview
Problem
Conventional bond pad configurations in non-volatile memory devices, such as 3D NAND Flash memory devices, hinder performance improvements and reduce feature size reductions due to their design limitations in microelectronic device architecture.
Innovation Solution
The proposed solution involves a microelectronic device design with a conductive pad tier configuration where first conductive pads are positioned outside the memory array region and second conductive pads are placed within the logic region, allowing for improved electrical connectivity and reduced size, while maintaining performance advantages and simplified fabrication.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If conventional bond pad configurations are used with bond wires extending between bond pads and conductive contacts, then electrical connectivity is achieved, but the device size cannot be reduced and performance improvements are hampered
Solution Approach 1:
The patent extracts and eliminates the bond wire interconnection structure from the device. By integrating the conductive pad tier directly into the semiconductor die and forming conductive contacts that extend through the stack structure to connect with external circuitry, the invention removes the external bond wires and bond pads, thereby reducing device size while maintaining electrical connectivity
Solution Approach 2:
The patent transitions from a two-dimensional planar arrangement with peripheral bond pads to a three-dimensional vertical architecture. Conductive pads are positioned at different vertical levels (first conductive pads outside the memory array region, second conductive pads within the logic region) and connect through vertical conductive contacts, enabling compact integration without compromising electrical connection
2Reliability
If conventional bond pad configurations are used along the perimeter of the die, then electrical connection to external circuitry is established, but feature size reductions are impeded
Solution Approach 1:
The invention moves electrical connection points from the two-dimensional perimeter to a three-dimensional configuration within the die body. First conductive pads are positioned outside the memory array region while second conductive pads are placed within the logic region, allowing feature miniaturization while maintaining necessary electrical connections through vertical conductive paths
3Quantity of substance
If vertical memory array architectures are used to increase memory density, then more memory cells fit in a unit of die area, but conventional bond pad configurations still hamper performance improvements
Solution Approach 1:
The patent removes the conventional bond pad and bond wire infrastructure that limits performance. By integrating conductive pads directly into the vertical memory array structure and forming conductive contacts through the stack, the invention eliminates the performance bottleneck created by external interconnections while preserving the high memory density achieved through vertical stacking
Solution Approach 2:
The invention merges the function of bond pads and bond wires into the integrated circuit structure itself. Conductive pads and conductive contacts are formed as part of the same fabrication process that creates the vertical memory array, combining memory storage and electrical interconnection functions into a unified structure that enables both high density and improved performance
Data Source
AI summary
A microelectronic device comprises a base structure, a memory array overlying the base structure, and a conductive pad tier overlying the memory array. The base structure comprises a logic region including logic devices. The memory array comprises vertically extending strings of memory cells within a horizontal area of the logic region of the base structure. The conductive pad tier comprises first conductive pads substantially outside of the horizontal area of the logic region of the base structure, and second conductive pads horizontally neighboring the first conductive pads and within the horizontal area of the logic region of the base structure. Memory devices and electronic systems are also described.