Conductive Pads with Segmented Metal Density for PoP Stress Reduction

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Solution Overview

Problem

The semiconductor industry faces challenges in reducing stress and manufacturing defects in Package-on-Package (PoP) technology due to high metal density in conductive pads, leading to issues like stress-induced sidewall peeling and thermal cycle test failures.

Innovation Solution

The implementation of a redistribution structure with conductive pads having reduced metal density, featuring openings filled with insulating material to alleviate stress and improve electrical routing between overlapping through vias, which are oriented to overlap in a top-down view, thereby reducing interference and stress between them.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Reliability

If high metal density is used in conductive pads, then electrical conductivity is improved, but stress-induced sidewall peeling and manufacturing defects increase

Engineering Contradiction:
Improveelectrical conductivityVSAvoidstress-induced sidewall peeling
Core Design Contradiction:
ReliabilityVSObject-generated harmful factors

Solution Approach 1:

The conductive pad is segmented into multiple regions with different metal densities. A first conductive region has higher metal density for optimal electrical conductivity, while a second conductive region has lower metal density to reduce stress. This segmentation allows the pad to simultaneously achieve good electrical performance and reduced stress-induced defects.

Inventive Principle:
Principle #1Segmentation

Solution Approach 2:

Different regions of the conductive pad are assigned different local qualities in terms of metal density. The first conductive region maintains high metal density for electrical performance, while the second conductive region uses reduced metal density to minimize stress. This local quality variation resolves the contradiction between conductivity and stress reduction.

Inventive Principle:
Principle #3Local quality

2Object-generated harmful factors

If metal density in conductive pads is reduced, then stress-induced defects are minimized, but electrical conductivity decreases

Engineering Contradiction:
Improvestress-induced sidewall peelingVSAvoidelectrical conductivity
Core Design Contradiction:
Object-generated harmful factorsVSReliability

Solution Approach 1:

The conductive pad structure is divided into multiple conductive regions with different metal densities. This segmentation enables the structure to maintain overall conductivity while reducing stress in specific areas, thereby preventing sidewall peeling without sacrificing electrical performance.

Inventive Principle:
Principle #1Segmentation

Solution Approach 2:

The conductive pad exhibits non-uniform metal density distribution, with high-density regions for conductivity and low-density regions for stress reduction. This local quality differentiation allows the pad to simultaneously satisfy both electrical and mechanical requirements.

Inventive Principle:
Principle #3Local quality

3Productivity

If through vias are oriented to overlap in top-down view, then electrical routing efficiency is improved, but interference and stress between vias increase

Engineering Contradiction:
Improveelectrical routing efficiencyVSAvoidinterference and stress between vias
Core Design Contradiction:
ProductivityVSObject-generated harmful factors

Solution Approach 1:

The overlapping via structure is segmented into multiple conductive regions, each with optimized metal density. This segmentation allows the via structure to maintain compact routing while reducing stress concentration and interference between adjacent vias through localized metal density control.

Inventive Principle:
Principle #1Segmentation

Solution Approach 2:

The via structure uses non-uniform metal density distribution in different regions to balance routing efficiency and stress reduction. High-density regions maintain electrical performance, while low-density regions reduce stress and interference, enabling overlapping via orientation without excessive harmful effects.

Inventive Principle:
Principle #3Local quality

Data Source

PatentUS10629537B2Conductive vias in semiconductor packages and methods of forming same
Publication Date: 2020.04.21 TAIWAN SEMICONDUCTOR MANUFACTURING CO LTD
  • US10629537B2 patent drawing
  • US10629537B2 patent drawing
  • US10629537B2 patent drawing

AI summary

An embodiment package includes a first integrated circuit die encapsulated in a first encapsulant; a first through via extending through the first encapsulant; and a conductive pad disposed in a dielectric layer over the first through via and the first encapsulant. The conductive pad comprises a first region electrically connected to the first through via and having an outer perimeter encircling an outer perimeter of the first through via in a top down view. The package further includes a first dielectric region extending through the first region of the conductive pad. A conductive material of the first region encircles the first dielectric region in the top down view.