Conductive Pillar Memory Structure for High-Density 3D FeFET Arrays
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Solution Overview
Problem
As semiconductor devices continue to shrink in feature size to increase integration density, challenges arise in maintaining reliable and efficient memory storage and retrieval due to the limitations of current memory technologies in managing smaller dimensions and higher densities.
Innovation Solution
A 3D memory array is developed using ferroelectric field effect transistors (FeFETs) with vertically stacked memory cells, incorporating a ferroelectric material as a gate dielectric and an oxide semiconductor channel region, allowing for increased density and improved read/write operations through controlled polarization and voltage application.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Quantity of substance
If minimum feature size is reduced to increase integration density, then more components can be integrated into a given area, but manufacturing precision and reliability deteriorate
Solution Approach 1:
The patent transitions from planar 2D memory architecture to three-dimensional vertical stacking architecture. Multiple memory layers are stacked vertically with conductive pillars extending through dielectric layers, enabling memory cells to be arranged in three dimensions rather than confined to a single plane. This dimensional transition allows significant increase in integration density while maintaining acceptable feature size control and manufacturing precision.
Solution Approach 2:
The patent implements a nested structure where conductive pillars are surrounded by channel layers, which are in turn surrounded by memory material layers, all within a vertically stacked multi-layer architecture. This nested arrangement allows multiple functional components to be integrated in a compact vertical space, increasing component density without proportionally reducing feature sizes.
2Quantity of substance
If minimum feature size is reduced to increase integration density, then more components can be integrated into a given area, but device complexity increases
Solution Approach 1:
The patent divides the memory device into multiple discrete functional layers including dielectric layers, conductive pillars, channel layers, and memory material layers. Each layer can be independently fabricated and controlled, allowing complex three-dimensional functionality to be achieved through sequential deposition and patterning of simpler individual layers rather than attempting to fabricate the entire complex structure in one process.
Solution Approach 2:
By moving to vertical stacking, the patent distributes device complexity across multiple layers in the vertical dimension rather than concentrating it in a single planar layer. This allows each individual layer to maintain relatively simple fabrication processes while the overall device achieves high integration density through vertical integration.
3Ease of manufacture
If traditional memory technology is used in smaller dimensions, then manufacturing is simpler, but reliability and performance deteriorate
Solution Approach 1:
The patent employs composite material structures including ferroelectric material combined with oxide semiconductor channel layers, surrounded by dielectric and conductive materials. This composite architecture enables the device to maintain reliability through the functional properties of each material layer while being fabricated using extended conventional semiconductor processes, thus achieving both reliability and ease of manufacture.
Solution Approach 2:
The patent utilizes ferroelectric material properties where polarization state can be switched and maintained, providing reliable non-volatile memory storage. By changing the physical state parameter (polarization direction) rather than relying solely on dimensional scaling, the device maintains high reliability even as feature sizes are reduced and integration density is increased.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This solution enhances memory device density and performance by enabling faster operation speeds and reduced error rates in data storage and retrieval, addressing the limitations of traditional memory technologies in smaller feature sizes.
Implementation Method 1
A memory device includes a ferroelectric material layer surrounding a channel layer
Implementation Method 2
ferroelectric field effect transistors (FeFETs) with vertically stacked memory cells, incorporating a ferroelectric material as a gate dielectric and an oxide semiconductor channel region
Data Source
AI summary
A first conductive pillar is formed. A plurality of second conductive pillars are formed at different sides of the first conductive pillar. A plurality of dielectric pillars are respectively formed between the first conductive pillar and the plurality of second conductive pillars. A channel layer is formed to continuously surround the first conductive pillar, the plurality of second conductive pillars and the plurality of dielectric pillars. A memory material layer is formed to surround the channel layer.