Conductive Pillar Layout for Uniform Semiconductor Bump Heights
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Solution Overview
Problem
The challenge in IC packaging lies in the variation of bump heights across the chip and substrate, caused by differences in plating current density and chip size, leading to inconsistent solder joints and potential signal errors and chip failure due to solder bridging and wetting issues.
Innovation Solution
The solution involves designing bump structures with varying widths across different regions of the chip and substrate to maintain consistent bump heights, using a combination of copper and solder layers with specific thickness ranges, and employing under bump metallurgy layers to control plating processes, ensuring uniform bonding without solder bridging.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Ease of manufacture
If uniform bump structures are used across the chip, then manufacturing is simple, but bump height variation occurs due to plating current density differences
Solution Approach 1:
The patent applies local quality by varying the bump structure characteristics (such as opening size, copper layer thickness, or solder layer thickness) in different regions of the chip. Specifically, bumps near the center have different structural parameters than bumps near the edges to compensate for the higher plating current density at the center, thereby achieving uniform bump heights across the entire chip surface.
2Area of stationary object
If larger chip size is used, then more circuits can be integrated, but bump height variation increases
Solution Approach 1:
The patent divides the chip into different regions (e.g., center region and edge regions) and assigns different bump structural characteristics to each region. This allows the chip to be scaled up in area while maintaining bump height consistency through localized structural adjustments that account for the varying plating current density across the larger surface area.
3Ease of manufacture
If inconsistent bump heights are present, then manufacturing is easier, but solder bridging and wetting issues occur
Solution Approach 1:
The patent implements local quality control in the bump structure design, where structural parameters are adjusted in different regions to achieve uniform bump heights. This uniformity prevents solder bridging and wetting issues during the packaging process, thereby improving solder joint quality and overall device reliability while maintaining ease of manufacture through a systematic design approach.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach results in consistent bump heights across the packaged chip and substrate, preventing solder bridging and signal errors, and facilitating proper underfill formation, thereby enhancing the reliability and stability of the chip package.
Implementation Method 1
Each of the conductive pillars includes a copper layer and a solder layer. The copper layer has a thickness in a range from about 3 μm to about 25 μm, and the solder layer has a thickness in a range from about 3 μm to about 15 μm.
Data Source
AI summary
A semiconductor device includes a first substrate and a second substrate. The semiconductor device includes a plurality of conductive pillars between the first and second substrates. The plurality of conductive pillars includes a first conductive pillar having a first width, wherein the first width is substantially uniform along an entire first height of the first conductive pillar, a second conductive pillar having a second width, wherein the second width is substantially uniform along an entire second height of the second conductive pillar, the first width is different from the second width, and the entire first height is equal to the entire second height, and a third conductive pillar having a third width, wherein the third width is substantially uniform along an entire third height of the third conductive pillar, and the third conductive pillar is between the first conductive pillar and the second conductive pillar in the first direction.