Conductive Pillar Layout for Reliable Fine-Pitch Chip Interconnects
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Solution Overview
Problem
The challenge of forming reliable semiconductor devices at smaller sizes is exacerbated by the increasing complexity and difficulty of fabrication processes as feature sizes continue to decrease, affecting the reliability and efficiency of semiconductor integrated circuits.
Innovation Solution
A chip structure is developed with a conductive pillar and conductive via structure, utilizing thicker conductive lines and conductive vias made of copper to reduce stress migration and electromigration, and incorporating a design that allows for improved planarity and alignment tolerance, thereby enhancing the stability and reliability of the semiconductor device.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If feature sizes continue to decrease to increase functional density, then production efficiency and cost are improved, but fabrication process complexity and difficulty increase
Solution Approach 1:
The patent changes the material parameter from traditional copper to tungsten for conductive pillars and vias. This parameter change enables the fabrication process to work effectively at smaller feature sizes while maintaining reliability, thus resolving the contradiction between increasing functional density and managing fabrication complexity.
Solution Approach 2:
The patent employs a composite structure with tungsten conductive pillars embedded in dielectric material, and tungsten-filled vias. This composite approach allows different materials to be optimized for different functions, enabling reliable miniaturization without proportionally increasing fabrication complexity.
2Area of stationary object
If feature sizes continue to decrease to increase functional density, then chip area is reduced, but device reliability deteriorates
Solution Approach 1:
The patent changes the material parameter from copper to tungsten, which has superior mechanical strength and lower stress migration characteristics. This parameter change maintains device reliability even as feature sizes decrease and chip area is reduced.
Solution Approach 2:
The patent uses tungsten, which can be deposited as thin films and formed into precise structures that are reliable at small scales. This material choice enables reliable miniaturization where traditional materials would fail.
Data Source
AI summary
A chip structure is provided. The chip structure includes an insulating layer over a first conductive line. The chip structure includes a conductive pillar over and passing through the insulating layer. The conductive pillar is formed in one piece, the conductive pillar is connected to the first conductive line, a first sidewall of the first conductive line extends across a second sidewall of the conductive pillar in a top view of the first conductive line and the conductive pillar, the conductive pillar vertically overlaps a first portion of the first conductive line, a first linewidth of the first portion of the first conductive line is less than a width of the conductive pillar, and the first linewidth and the width are measured along an axis perpendicular to a first longitudinal axis of the first portion of the first conductive line.