Conductive Pillar Chip Package Layout for Thin Multi-Chip Interconnects
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Solution Overview
Problem
The challenge in semiconductor device packaging is to reduce the thickness of chip package structures with multiple chips while maintaining efficient signal transmission and structural integrity.
Innovation Solution
A chip package structure is formed with conductive pillars and bumps, where the conductive pillars are formed over conductive pads and connected to chip structures, and a molding material surrounds these components, allowing for further thinning of the substrate and improving signal transmission efficiency by increasing the density of conductive bumps.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Adaptability or versatility
If multiple chips are integrated in a chip package structure, then functionality is improved, but thickness increases
Solution Approach 1:
The patent transitions from vertical stacking to lateral integration by arranging multiple chip structures side-by-side on the same substrate plane. This dimensional reorganization allows multiple functional chips to coexist without increasing package thickness, as they are positioned horizontally rather than vertically stacked.
Solution Approach 2:
The package structure is segmented into multiple independent chip structures (first chip structure, second chip structure, etc.) that can be individually designed and positioned. Each chip structure contains its own functional elements and is separated by spacing, allowing independent optimization while maintaining overall package thinness through lateral arrangement.
2Reliability
If conductive bumps density is increased, then signal transmission efficiency is improved, but manufacturing complexity increases
Solution Approach 1:
The patent implements non-uniform spacing of conductive bumps, with different pitch values in different regions (first pitch in first region, second pitch in second region). This local variation allows higher bump density in critical signal transmission areas while maintaining lower density in less critical areas, optimizing signal efficiency without uniformly increasing manufacturing complexity across the entire package.
Data Source
AI summary
A chip package structure includes a first chip structure having a first substrate and a first interconnect layer over the first substrate and a second chip structure over the first interconnect layer. The chip package structure also includes a conductive pillar over the first interconnect layer and a molding layer over the first interconnect layer, the first chip structure, the second chip structure, and the conductive pillar. The chip package structure further includes a conductive bump embedded in the molding layer and over a top surface of the conductive pillar. A portion of the molding layer is between the conductive bump and a peripheral portion of the top surface of the conductive pillar. The conductive bump extends to a central portion of the top surface of the conductive pillar. The portion of the molding layer tapers toward the central portion of the top surface of the conductive pillar.