Semiconductor Package Structure Using Conductive Pillars for Chip Stacking
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Solution Overview
Problem
Current semiconductor packages face challenges in efficiently increasing integration density and mounting multiple semiconductor chips, particularly in small, light, and multi-functional electronic devices, where traditional methods struggle to effectively stack and connect chips for enhanced performance.
Innovation Solution
The semiconductor package design features an upper substrate with conductive pillars and pads that connect lower and upper semiconductor chips, allowing for vertical and horizontal stacking, and includes intermediate substrates like interposers or redistribution layers to facilitate electrical connections, enabling easy mounting and increased integration density.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Manufacturing precision
If traditional semiconductor packaging methods are used, then manufacturing process is simple, but integration density cannot be increased efficiently
Solution Approach 1:
The patent transitions from traditional planar (2D) chip arrangement to vertical (3D) stacking configuration. Multiple semiconductor chips are stacked in the vertical direction with conductive pillars extending through substrate layers, enabling efficient use of three-dimensional space and significantly increasing integration density within a compact footprint.
Solution Approach 2:
The patent implements a nested structure where semiconductor chips are embedded within substrate layers. The chips are positioned between upper and lower substrate portions, with conductive pillars penetrating through the substrate to establish electrical connections. This nesting approach allows multiple functional layers to be integrated vertically.
2Manufacturing precision
If multiple semiconductor chips are stacked vertically, then integration density increases, but mounting difficulty increases
Solution Approach 1:
The patent employs preliminary bonding of semiconductor chips to the substrate before final package assembly. The chips are pre-positioned and bonded to the lower substrate portion with conductive pillars extending upward, preparing the structure for subsequent upper substrate attachment. This preliminary arrangement simplifies the overall mounting process by establishing connections in advance.
Solution Approach 2:
The substrate acts as an intermediary component that facilitates the connection between stacked semiconductor chips. The substrate with conductive pillars serves as a mediator that enables electrical and mechanical coupling between lower and upper chips, simplifying the mounting process by providing a standardized interface structure.
3Reliability
If conductive pillars are added for chip connections, then electrical connectivity improves, but device complexity increases
Solution Approach 1:
The conductive pillars serve multiple functions simultaneously: they provide electrical connection between stacked chips, act as mechanical support structures, and enable thermal conduction pathways. This multi-functionality reduces the need for separate components and simplifies the overall connection structure despite the vertical stacking complexity.
Solution Approach 2:
The patent merges the electrical connection function with the structural support function into a single conductive pillar element. Rather than using separate wires for electrical connection and mechanical support, the conductive pillars combine both roles, reducing the number of discrete components needed in the stacked chip architecture.
Data Source
AI summary
A semiconductor package includes an upper substrate having a first surface and a second surface which are opposite to each other, a lower semiconductor chip disposed on the first surface of the upper substrate, a plurality of conductive pillars disposed on the first surface of the upper substrate at at least one side of the lower semiconductor chip, and an upper semiconductor chip disposed on the second surface of the upper substrate. The lower semiconductor chip and the plurality of conductive pillars are connected to the first surface of the upper substrate, and the upper semiconductor chip is connected to the second surface of the upper substrate.