Conductive-Pillar Nonvolatile Memory for Low-Voltage Write and Erase
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Solution Overview
Problem
Existing nonvolatile memory devices face challenges in efficiently performing write and erase operations at low voltages, leading to issues such as heat generation, stress, ion movement, and leakage current, particularly in next-generation 3D NAND structures, which affect density and reliability.
Innovation Solution
A nonvolatile memory device design incorporating a conductive pillar, resistance change layer, semiconductor layer, and gate insulating layer with independent voltage application through first and second bit lines, allowing for controlled application of voltages with small intensity differences to facilitate efficient write and erase operations, reducing heat and stress, and preventing ion movement.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If conventional voltage application methods are used in existing nonvolatile memory devices, then write and erase operations can be performed, but heat generation and stress increase, leading to device deterioration and reliability issues
Solution Approach 1:
The voltage application is segmented into two independent paths: a first bit line applies a first voltage to the conductive pillar, while a second bit line applies a second voltage to the semiconductor layer. This segmentation allows independent optimization of voltage profiles, enabling write and erase operations with reduced voltage intensity differences, thereby minimizing heat generation and stress that cause device deterioration
Solution Approach 2:
The patent changes the voltage parameters by applying different voltage intensities through separate bit lines. The first voltage and second voltage can be independently controlled, allowing the voltage difference to be kept small during operations. This parameter optimization reduces the thermal and mechanical stress on the resistance change layer, improving device reliability while maintaining operation effectiveness
2Productivity
If high voltage is applied to perform write and erase operations, then operation effectiveness is maintained, but ion movement and leakage current increase, affecting memory density and reliability
Solution Approach 1:
The voltage application is segmented into two independent paths: a first bit line applies a first voltage to the conductive pillar, while a second bit line applies a second voltage to the semiconductor layer. This segmentation allows independent optimization of voltage profiles, enabling write and erase operations with reduced voltage intensity differences, thereby minimizing heat generation and stress that cause device deterioration
Solution Approach 2:
The patent changes the voltage parameters by applying different voltage intensities through separate bit lines. The first voltage and second voltage can be independently controlled, allowing the voltage difference to be kept small during operations. This parameter optimization reduces the thermal and mechanical stress on the resistance change layer, improving device reliability while maintaining operation effectiveness
3Reliability
If voltage intensity difference is reduced to minimize heat and stress, then device reliability improves, but operation efficiency may be compromised
Solution Approach 1:
The voltage application is segmented into two independent paths: a first bit line applies a first voltage to the conductive pillar, while a second bit line applies a second voltage to the semiconductor layer. This segmentation allows independent optimization of voltage profiles, enabling write and erase operations with reduced voltage intensity differences, thereby minimizing heat generation and stress that cause device deterioration
Solution Approach 2:
The patent changes the voltage parameters by applying different voltage intensities through separate bit lines. The first voltage and second voltage can be independently controlled, allowing the voltage difference to be kept small during operations. This parameter optimization reduces the thermal and mechanical stress on the resistance change layer, improving device reliability while maintaining operation effectiveness
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
The proposed design enables reliable and high-density memory operations with reduced voltage requirements, minimizing device deterioration and improving scalability, suitable for neuromorphic computing platforms and neural networks.
Implementation Method 1
a resistance change layer surrounding a side surface of the conductive pillar
Data Source
AI summary
Provided are a nonvolatile memory device and an operating method thereof. The nonvolatile memory device may include a conductive pillar, a resistance change layer surrounding a side surface of the conductive pillar, a semiconductor layer surrounding a side surface of the resistance change layer, a gate insulating layer surrounding a side surface of the semiconductor layer, and a plurality of insulating patterns and a plurality of gate electrodes alternately arranged along a surface of the gate insulating layer. The plurality of insulating patterns and the plurality of gate electrodes may surround a side surface of the gate insulating layer.