Conductive Pillar Packaging for Clean RDL Via Connection

Resolve Bottlenecks,
Find Innovative Solutions
Generate Solutions

Solution Overview

Problem

As semiconductor devices become highly integrated and miniaturized, the reduced interval between solder balls makes handling difficult, and existing fan-out wafer-level packaging techniques struggle to effectively expose conductive pillars during encapsulant grinding, leading to contamination and reliability issues.

Innovation Solution

A method of manufacturing a semiconductor package involving the formation of conductive pillars with their upper surfaces below the semiconductor chip's surface, where an encapsulant is planarized to expose the pillars, and a second redistribution structure is formed connected to these pillars, including an interconnection pattern and a connection via with a wider upper surface than lower surface, to prevent contamination and enhance reliability.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Reliability

If the encapsulant is ground to expose conductive pillars, then the pillars become accessible for connection, but the pillars become contaminated during the grinding process

Engineering Contradiction:
Improveconnection reliabilityVSAvoidcontamination
Core Design Contradiction:
ReliabilityVSObject-affected harmful factors

Solution Approach 1:

The conductive pillars are formed to extend below the upper surface of the semiconductor chip before encapsulation. This preliminary positioning allows the encapsulant to be ground away to expose the pillars without requiring the pillars to be exposed during the grinding process itself, thus preventing contamination while achieving accessibility for connection.

Inventive Principle:
Principle #10Preliminary action

Solution Approach 2:

The encapsulant serves as an intermediary protective layer that covers the conductive pillars during manufacturing and handling. By designing the pillars to extend below the chip surface, the encapsulant can be selectively removed to expose only the necessary portions of the pillars for connection, minimizing exposure time and contamination risk.

Inventive Principle:
Principle #24Intermediary (Mediator)

2Ease of operation

If the conductive pillars are positioned at the same level as the semiconductor chip surface, then they are easily accessible, but the encapsulant cannot be uniformly ground

Engineering Contradiction:
Improvepillar accessibilityVSAvoidencapsulant grinding uniformity
Core Design Contradiction:
Ease of operationVSManufacturing precision

Solution Approach 1:

The conductive pillars are positioned with their upper surfaces at a lower level than the upper surface of the semiconductor chip, creating a localized depth difference. This allows the encapsulant to be uniformly ground across the entire surface while the pillars remain partially exposed at specific locations where connections are needed, achieving both grinding uniformity and pillar accessibility.

Inventive Principle:
Principle #3Local quality

3Volume of moving object

If the interval between solder balls is reduced for miniaturization, then device size is reduced, but handling becomes difficult

Engineering Contradiction:
Improvedevice sizeVSAvoidhandling ease
Core Design Contradiction:
Volume of moving objectVSEase of operation

Solution Approach 1:

Instead of reducing the interval between solder balls in the horizontal plane, the invention moves the connection interface to a different dimension by positioning conductive pillars vertically below the chip surface. This allows miniaturization in the horizontal plane while maintaining handling ease through the vertical exposure of connection points after encapsulant removal.

Inventive Principle:
Principle #17Another dimension (Dimensionality change)

Data Source

PatentUS12027495B2Semiconductor devices having a conductive pillar and methods of manufacturing the same
Publication Date: 2024.07.02 SAMSUNG ELECTRONICS CO LTD
  • US12027495B2 patent drawing
  • US12027495B2 patent drawing
  • US12027495B2 patent drawing

AI summary

A method of manufacturing a semiconductor package includes forming a first redistribution structure, forming a plurality of conductive pillars on the first redistribution structure, mounting the first semiconductor chip on the first redistribution structure, forming an encapsulant configured to cover an upper surface of the first redistribution structure, the plurality of conductive pillars, and the first semiconductor chip, planarizing the encapsulant, exposing the plurality of conductive pillars by forming an opening in the planarized encapsulant, and forming a second redistribution structure connected to the plurality of conductive pillars on the first semiconductor chip and the encapsulant. Upper surfaces of the plurality of conductive pillars are located at a lower level than the upper surface of the first semiconductor chip, and an upper surface of a connection via included in the second redistribution structure has a width greater than a width of a lower surface of the connection via.