Conductive Pillar Structure With Selective Etching for Lower Resistance
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Solution Overview
Problem
As semiconductor structures shrink, the high resistance of conductive pillars in the core area hinders effective electrical performance improvement, particularly in areas like the core area where device structures such as word-line drivers are located.
Innovation Solution
A method is employed to manufacture semiconductor structures by forming a mask layer over conductive pillars, etching a portion of the third conductive pillar to create a lower and upper pillar with different surface areas, and filling a groove with a cover layer to reduce resistance while avoiding short circuits.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If the process node is shrunk to increase integration, then cost is reduced and power consumption is lowered, but the resistance of conductive pillars in the core area increases, hindering electrical performance improvement
Solution Approach 1:
The patent applies different processing treatments to different areas of the semiconductor device. Specifically, the core area conductive pillars are selectively etched to create a tapered structure with larger cross-sectional area at the base, while peripheral area pillars maintain their original cylindrical shape. This local differentiation reduces resistance in the core area without affecting other regions, directly addressing the electrical performance issue while maintaining overall device integration benefits
2Reliability
If a mask layer is formed and etching is performed on the third conductive pillar, then resistance is reduced and electrical performance is enhanced, but the manufacturing process complexity increases
Solution Approach 1:
The patent segments the conductive pillars into different groups based on their location and electrical requirements. The core area pillars (third conductive pillars) are separated from peripheral area pillars through selective masking and etching processes. This segmentation allows targeted resistance reduction in critical areas while maintaining simplicity in non-critical areas, balancing electrical performance improvement with manufacturing complexity
Solution Approach 2:
The patent introduces a mask layer as an intermediary element to enable selective etching of core area conductive pillars. This mask layer acts as a mediator that protects peripheral pillars while allowing the core pillars to be tapered, achieving the desired resistance reduction without requiring complex direct manipulation of each pillar. The mask layer is subsequently removed, leaving the modified pillar structure
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach reduces the resistance of the conductive pillars in the core area, enhancing electrical performance and optimizing the manufacturing process by maintaining the profiles of other pillars and preventing erroneous electrical connections.
Implementation Method 1
A mask layer is formed, in which the mask layer covers the dielectric layer, the first conductive pillar, the second conductive pillar and a portion of the third conductive pillar, and exposes a top surface of a portion of the third conductive pillar
Implementation Method 2
A portion of a thickness of the third conductive pillar is etched by using the mask layer as a mask to form a third lower conductive pillar and a third upper conductive pillar stacked on one another
Data Source
AI summary
A method for manufacturing a semiconductor structure includes the following operations. A base and a dielectric layer arranged on the base are provided. A first conductive pillar, a second conductive pillar and a third conductive pillar arranged in the dielectric layer are formed. A mask layer is formed. A portion of a thickness of the third conductive pillar is etched by using the third mask layer as a mask to form a third lower conductive pillar and a third upper conductive pillar stacked on one another, in which the third upper conductive pillar, the third lower conductive pillar and the dielectric layer are configured to form at least one groove. A cover layer filling the at least one groove is formed, in which the cover layer exposes the top surface of the third upper conductive pillar.