Conductive Pillar Interconnects for Dense Semiconductor Packaging
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Solution Overview
Problem
The semiconductor industry faces challenges in miniaturizing packages while maintaining high functional density and reliability, particularly due to issues with solder joint size and the risk of electrical shorts in Integrated Fan Out (InFO) packages combined with Wafer Level Packaging (WLP) technology.
Innovation Solution
The use of conductive pillars to connect redistribution structures to routing substrates reduces the amount of solder needed, minimizing the risk of electrical shorts and improving reliability by allowing for a higher density of connections and incorporating additional functionality such as integrated passive devices or voltage regulators.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If traditional solder joint connections are used in InFO packages, then electrical connections can be established, but the risk of electrical shorts and bridging increases
Solution Approach 1:
The patent introduces conductive pillars as intermediary structures between the redistribution layer and routing substrate. These pillars serve as mediators that establish electrical connections while physically separating the solder joints, thereby reducing the risk of electrical shorts and bridging between adjacent connections.
Solution Approach 2:
The patent transitions from planar solder joint connections to three-dimensional structures by introducing vertical conductive pillars. This dimensional change allows connections to be stacked vertically, reducing lateral spacing requirements and minimizing the risk of electrical shorts between adjacent connections.
2Area of stationary object
If package size is reduced for miniaturization, then smaller packages are achieved, but the number of input/output pads is limited
Solution Approach 1:
The patent utilizes vertical stacking with conductive pillars to create three-dimensional interconnect structures. This allows multiple input/output pads to be connected through vertical pathways rather than requiring lateral spacing, enabling high functional density within a reduced package footprint.
Solution Approach 2:
The patent segments the interconnection function into multiple independent conductive pillars, each handling specific signal paths. This segmentation allows for higher density of connections by distributing I/O pads across multiple vertical interconnect levels, increasing adaptability without expanding package area.
3Reliability
If more solder is used to ensure reliable connections, then connection reliability improves, but the risk of bridging and deformation increases
Solution Approach 1:
The conductive pillars act as intermediaries that bear the mechanical and electrical load, allowing reduced solder volumes. The pillars provide structural support and electrical conductivity, enabling the use of smaller solder joints that are less prone to bridging and deformation while maintaining connection reliability.
Solution Approach 2:
The patent changes the physical parameters of the connection structure by introducing conductive pillars with controlled dimensions and materials. This parameter change allows optimization of solder joint size, reducing the amount of solder needed while maintaining reliability and minimizing bridging risks through precise dimensional control.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach enables smaller solder joints, reduces the risk of bridging and deformation, and increases connection density, thereby enhancing the performance and reliability of semiconductor packages while allowing for additional functional integration.
Implementation Method 1
The use of conductive pillars to connect redistribution structures to routing substrates reduces the amount of solder needed
Implementation Method 2
plating conductive pillars extending from a first side of the redistribution structure
Data Source
AI summary
A semiconductor package includes an interconnect structure including a redistribution structure, an insulating layer over the redistribution structure, and conductive pillars on the insulating layer, wherein the conductive pillars are connected to the redistribution structure, wherein the interconnect structure is free of active devices, a routing substrate including a routing layer over a core substrate, wherein the interconnect structure is bonded to the routing substrate by solder joints, wherein each of the solder joints bonds a conductive pillar of the conductive pillars to the routing layer, an underfill surrounding the conductive pillars and the solder joints, and a semiconductor device including a semiconductor die connected to a routing structure, wherein the routing structure is bonded to an opposite side of the interconnect structure as the routing substrate.