Conductive Pillar Chip Structure for Reliable Solder Bump Bonding

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Solution Overview

Problem

The challenge of forming reliable semiconductor devices at smaller sizes is exacerbated by the increasing complexity of fabrication processes as feature sizes continue to decrease, making it difficult to maintain processing reliability and efficiency.

Innovation Solution

A chip package structure is developed with a conductive via structure and conductive lines that include a thicker top metal wiring layer and conductive pillars with protruding locking portions to enhance bonding reliability and reduce stress migration, using materials like copper and silicon nitride to improve adhesion and withstand thermal expansion mismatches.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Productivity

If feature sizes continue to decrease to increase functional density, then production efficiency and cost are improved, but fabrication process complexity and reliability deteriorate

Engineering Contradiction:

Improveproduction efficiencyVSAvoidfabrication process reliability

Core Design Contradiction:

ProductivityVSReliability

Solution Approach 1:

The conductive pillar is divided into multiple materials with different properties: a first material (e.g., copper) for electrical conductivity and a second material (e.g., tungsten or cobalt) for mechanical strength and stress resistance. This segmentation allows each material to optimize its function, improving overall reliability while maintaining small feature sizes

Inventive Principle:

Principle #1Segmentation

Solution Approach 2:

The patent employs composite material structure where dissimilar materials are combined in the conductive pillar. The first material provides excellent electrical conductivity for signal transmission, while the second material provides mechanical robustness and resistance to stress migration, thereby maintaining fabrication reliability at scaled dimensions

Inventive Principle:

Principle #40Composite materials

2Productivity

If feature sizes continue to decrease to increase functional density, then production efficiency and cost are improved, but fabrication process complexity deteriorates

Engineering Contradiction:

Improveproduction efficiencyVSAvoidfabrication process complexity

Core Design Contradiction:

ProductivityVSDevice complexity

Solution Approach 1:

Inventive Principle:

Principle #1Segmentation

Solution Approach 2:

Different regions of the conductive pillar are assigned different materials based on local requirements: the lower portion or core uses high-conductivity material for electrical performance, while the upper portion or outer layer uses high-strength material for mechanical support. This local differentiation optimizes performance without uniformly increasing complexity

Inventive Principle:

Principle #3Local quality

3Area of stationary object

If conductive lines are narrowed to increase layout space, then area efficiency is improved, but bonding reliability deteriorates

Engineering Contradiction:

Improvelayout spaceVSAvoidbonding reliability

Core Design Contradiction:

Area of stationary objectVSReliability

Solution Approach 1:

The conductive pillar uses composite material structure where dissimilar materials are combined: a soft, highly conductive material (copper) combined with a hard, stress-resistant material (tungsten or cobalt). This allows the narrowed conductive line to maintain both electrical performance and mechanical bonding reliability, preventing stress migration even at reduced dimensions

Inventive Principle:

Principle #40Composite materials

Solution Approach 2:

The conductive pillar structure incorporates a material composition and geometry designed to preemptively resist stress migration before it can occur. The second material acts as a cushioning element that absorbs and distributes thermal and mechanical stresses, protecting the bonding interface from failure even when the conductive line is narrowed

Inventive Principle:

Principle #11Beforehand cushioning (Prior cushioning)

Data Source

PatentUS12463166B2Chip structure and method for forming the same

Publication Date: 2025.11.04 TAIWAN SEMICONDUCTOR MANUFACTURING CO LTD

AI summary

A chip structure is provided. The chip structure includes a substrate. The chip structure includes a first conductive line over the substrate. The chip structure includes an insulating layer over the substrate and the first conductive line. The chip structure includes a conductive pillar over the insulating layer. The chip structure includes a solder bump on the conductive pillar. The solder bump is in direct contact with the conductive pillar.