Conductive Pillar Via Formation in Semiconductor Packages
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Solution Overview
Problem
Conventional semiconductor package fabrication methods are inefficient due to slow laser drilling for forming vias, accumulation of residual materials, uneven via walls leading to poor conductive material attachment, increased complexity and cost, and limitations in miniaturization and low-profile requirements.
Innovation Solution
The method involves forming conductive pillars in a dielectric layer before encapsulation, eliminating the need for laser drilling and reducing the number of fabrication steps, which simplifies the process, reduces costs, and enhances reliability by using a CMP method to expose the pillars and embedding them within both the dielectric and encapsulating layers.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Manufacturing precision
If laser drilling is used to form vias, then vias can be formed to expose the redistribution layer, but the process is slow and time-consuming especially when the number of vias is large
Solution Approach 1:
The patent replaces the laser drilling process (thermal/optical system) with a chemical etching process using a patterned photoresist mask and etching solution. This substitution eliminates the slow laser drilling step while maintaining via formation capability, significantly improving fabrication productivity.
Solution Approach 2:
The patent applies a patterned photoresist mask before etching to predefine the via locations and shapes. This preliminary patterning action allows for rapid chemical etching without the need for slow laser drilling, as the etching process follows the pre-established mask pattern.
2Manufacturing precision
If laser drilling is used to form vias, then openings can be created, but residual materials accumulate at the bottom of the vias requiring additional cleaning processes
Solution Approach 1:
The chemical etching process with photoresist mask replaces laser drilling, eliminating the accumulation of residual materials at via bottoms. The chemical etching provides clean via walls without the melting and residue issues associated with laser drilling, thereby removing the need for additional cleaning processes.
3Manufacturing precision
If laser drilling is used to form vias, then openings can be created, but the walls of the vias become uneven leading to poor attachment of conductive materials
Solution Approach 1:
The chemical etching process with photoresist mask replacement produces vias with uniform, smooth walls that provide excellent surface area for conductive material attachment. This eliminates the uneven walls and peeling issues caused by laser drilling, significantly improving the reliability of conductive material bonding.
4Manufacturing precision
If laser drilling is used to form vias, then vias can be formed, but specialized equipment and alignment processes are required increasing fabrication cost
Solution Approach 1:
The patent replaces expensive laser drilling equipment and specialized alignment systems with standard photolithography and chemical etching equipment. The photoresist mask alignment uses conventional optical alignment methods that are already standard in semiconductor fabrication, thereby reducing equipment costs and simplifying the manufacturing process.
5Manufacturing precision
If laser drilling is used to form vias, then openings can be created, but heat affect zone damages the semiconductor element requiring via distance from the element
Solution Approach 1:
The chemical etching process with photoresist mask replaces laser drilling, eliminating the heat affect zone problem entirely. Chemical etching operates at ambient or moderate temperatures without generating the high heat that damages semiconductor elements, allowing vias to be formed immediately adjacent to the semiconductor element without any heat-related concerns.
6Ease of manufacture
If multiple carriers are bonded and removed during fabrication, then the semiconductor element can be processed, but the number of steps increases making the process time-consuming
Solution Approach 1:
The patent merges the via formation process with the carrier processing steps by performing photoresist patterning and chemical etching while the semiconductor element is mounted on the carrier. This integration eliminates the need for separate carrier bonding and removal steps, reducing the total number of fabrication steps and time.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach reduces the complexity and cost of the fabrication process, increases the reliability of the semiconductor package, allows for further miniaturization, and meets low-profile requirements by eliminating the need for laser drilling and alignment equipment.
Implementation Method 1
a polishing method is employed to remove a portion of the encapsulating layer
Data Source
AI summary
The present invention provides a package structure and fabrication method thereof. The method includes providing a first carrier having a metal layer; forming a dielectric layer on the metal layer; forming a plurality of conductive pillars embedded into the dielectric layer and protruding from a surface of the dielectric layer, and disposing an electronic component on the surface of the dielectric layer; forming an encapsulating layer on the dielectric layer to encompass the plurality of conductive pillars, the dielectric layer and the electronic component; removing a portion of the encapsulating layer and the first carrier such that two ends of each of the plurality of conductive pillars are exposed from the encapsulating layer and the dielectric layer. Therefore, the present invention effectively reduces manufacturing costs and the need for an opening process while manufacturing the conductive pillars can be eliminated.