Conductive Pillars Integrated Fan-Out Package Fabrication
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Solution Overview
Problem
The semiconductor industry faces challenges in simplifying the fabrication process of integrated fan-out packages, which are crucial for heterogeneous integration and future package reliability, due to complex processes and high costs associated with traditional chip-probing and packaging methods.
Innovation Solution
The process involves forming conductive pillars directly on the topmost patterned conductive layer without additional probing pads, enhancing adhesion and reducing resistivity, and using a protection layer to encapsulate the pillars, followed by a simplified chip-probing process and wafer dicing, then constructing an integrated fan-out package with conductive through insulator vias and redistribution circuits, ultimately forming a package-on-package structure.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If traditional chip-probing and packaging methods are used, then packaging reliability is achieved, but fabrication process complexity and cost increase
Solution Approach 1:
The patent extracts and eliminates the traditional probing pad structure from the semiconductor device. By forming conductive pillars directly on the interconnection structure without requiring separate probing pads, the invention removes an unnecessary structural element, thereby simplifying the fabrication process while maintaining packaging reliability through direct conductive connections
Solution Approach 2:
The patent merges the function of conductive pillars with the interconnection structure by forming the pillars directly on the topmost patterned conductive layer. This consolidation eliminates the need for separate probing pad structures and reduces the number of fabrication steps, achieving both process simplification and reliability maintenance
2Reliability
If traditional probing pads are used, then electrical connection is achieved, but adhesion and resistivity characteristics worsen
Solution Approach 1:
The patent applies preliminary action by forming the conductive pillars directly on the topmost patterned conductive layer of the interconnection structure before packaging. This direct formation approach establishes optimal adhesion from the beginning and ensures low resistivity connections, eliminating the need for intermediate probing pad structures that would compromise electrical characteristics
3Productivity
If simplified fabrication process is used, then manufacturing cost and time are reduced, but process reliability may worsen
Solution Approach 1:
The patent applies self-service by designing a fabrication process where conductive pillars are formed directly on the interconnection structure using standard semiconductor manufacturing techniques. This self-contained approach eliminates the need for additional probing pad fabrication steps while maintaining connection reliability, as the pillars integrate seamlessly with the existing interconnection architecture
Data Source
AI summary
A semiconductor device including an integrated circuit, a plurality of conductive pillars, and a protection layer is provided. The integrated circuit includes a semiconductor substrate and an interconnection structure covering the semiconductor substrate, wherein the interconnection structure includes a plurality of patterned conductive layers and a plurality of inter-dielectric layers stacked alternately, the topmost patterned conductive layer of the patterned conductive layers is covered by the topmost inter-dielectric layer of the inter-dielectric layers, and the topmost patterned conductive layer is exposed by a plurality of openings of the topmost inter-dielectric layer. The conductive pillars are disposed on the topmost patterned conductive layer exposed by the openings, and the conductive pillars are electrically connected to the topmost patterned conductive layer through the openings. The protection layer covers the integrated circuit and the conductive pillars. A method for fabricating the semiconductor device and a method for fabricating integrated fan-out packages including the semiconductor device are also provided.