Conductive Pillar Bump Structure for Chip Edge Warpage Relief
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Solution Overview
Problem
New packaging technologies for semiconductor dies face manufacturing challenges due to stress and warpage issues, which can lead to cracks and delamination, particularly in smaller package structures with increased density and functionality.
Innovation Solution
The solution involves forming conductive pillars with wider protruding portions at the edge and corner regions of semiconductor chips, which reduces stress and warpage by increasing the interface area and distributing bonding forces more evenly, thereby preventing cracks and delamination.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If new packaging technologies are used to increase density and functionality, then functional density is improved, but stress and warpage issues occur leading to cracks and delamination
Solution Approach 1:
The patent applies different geometries to conductive bumps based on their location: corner conductive bumps have larger cross-sectional areas than edge conductive bumps. This local differentiation addresses the stress concentration problem at corners while maintaining overall package density and functionality.
Solution Approach 2:
The patent changes the geometric parameters of conductive bumps, specifically making corner bumps larger than edge bumps. This parameter variation optimizes stress distribution across the package structure while preserving the increased density and functionality provided by new packaging technologies.
2Reliability
If conductive bumps are made larger to reduce stress, then stress distribution is improved, but package size increases
Solution Approach 1:
Instead of uniformly increasing all conductive bump sizes, the patent applies larger sizes only to corner bumps where stress concentration occurs. This localized approach improves stress distribution without proportionally increasing the overall package area.
Solution Approach 2:
The patent creates an asymmetric configuration where corner conductive bumps differ in size from edge conductive bumps. This asymmetry optimizes stress management at critical locations while minimizing the overall area occupied by the package structure.
Data Source
AI summary
A structure and a formation method of a semiconductor device are provided. The semiconductor device structure includes a semiconductor substrate and an interconnection structure over the semiconductor substrate. The semiconductor device structure also includes a first conductive pillar over the interconnection structure. The first conductive pillar has a first protruding portion extending towards the semiconductor substrate from a lower surface of the first conductive pillar. The semiconductor device structure further includes a second conductive pillar over the interconnection structure. The second conductive pillar has a second protruding portion extending towards the semiconductor substrate from a lower surface of the second conductive pillar. The first conductive pillar is closer to a center point of the semiconductor substrate than the second conductive pillar. A bottom of the second protruding portion is wider than a bottom of the first protruding portion.