Conductive Plate Bitline Parasitic Capacitance

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Solution Overview

Problem

Conventional DRAM arrays face issues with parasitic capacitance between adjacent bitlines, which becomes more problematic with increasing levels of integration, leading to inefficiencies and signal interference.

Innovation Solution

Incorporating voids between bitlines and a conductive plate operatively proximate to the bitlines to drain excess charge, reducing parasitic capacitance and alleviating signal interference.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Productivity

If bitlines are tightly packed to increase integration levels, then productivity and integration density improve, but parasitic capacitance between adjacent bitlines increases causing signal interference

Engineering Contradiction:

Improveintegration densityVSAvoidparasitic capacitance

Core Design Contradiction:

ProductivityVSObject-affected harmful factors

Solution Approach 1:

A conductive plate is introduced as an intermediary structure positioned between adjacent bitlines. This plate serves as a shield that manages the electromagnetic field interactions between closely spaced bitlines, allowing tight packing while controlling parasitic capacitance effects through its conductive nature and strategic positioning.

Inventive Principle:

Principle #24Intermediary (Mediator)

Solution Approach 2:

The harmful parasitic capacitance effect is extracted and managed by introducing a dedicated conductive plate structure. Rather than accepting the parasitic capacitance as an unavoidable byproduct of tight packing, the invention extracts this electromagnetic interaction and provides it a controlled structure that can be designed and positioned to minimize interference.

Inventive Principle:

Principle #2Taking out (Extraction)

2Reliability

If spacing between bitlines is increased to reduce parasitic capacitance, then signal integrity improves, but integration density and productivity decrease

Engineering Contradiction:

Improvesignal integrityVSAvoidintegration density

Core Design Contradiction:

ReliabilityVSProductivity

Solution Approach 1:

Instead of only adjusting the horizontal spacing between bitlines, the invention introduces a vertical dimension by positioning a conductive plate above or below the bitlines. This dimensional transition allows signal integrity to be improved through electromagnetic shielding in the vertical direction while maintaining tight horizontal packing for high integration density.

Inventive Principle:

Principle #17Another dimension (Dimensionality change)

3Ease of manufacture

If conventional DRAM array structure is used, then manufacturing simplicity is maintained, but parasitic capacitance causes signal interference and reliability issues

Engineering Contradiction:

Improvestructural simplicityVSAvoidsignal integrity

Core Design Contradiction:

Ease of manufactureVSReliability

Solution Approach 1:

The conductive plate structure serves multiple functions simultaneously: it acts as an electromagnetic shield to reduce parasitic capacitance, provides a reference potential for signal stability, and can be integrated into existing DRAM manufacturing processes using standard conductive layer deposition techniques. This multi-functionality maintains manufacturing simplicity while improving reliability.

Inventive Principle:

Principle #6Universality (Multi-functionality)

Applied Scientific Principles

This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.

Function Achieved in This Case

The solution effectively minimizes parasitic capacitance, enhancing signal integrity and allowing for tighter integration of bitlines without significant signal degradation.

Implementation Method 1

A problem which may be encountered with a conventional DRAM array is parasitic capacitance between adjacent bitlines

Methodology Applied

Scientific EffectParasitic capacitance: Capacitance

Data Source

PatentUS11139302B2Integrated assemblies comprising spaces between bitlines and comprising conductive plates operationally proximate the bitlines, and methods of forming integrated assemblies

Publication Date: 2021.10.05 MICRON TECHNOLOGY INC

AI summary

Some embodiments include an integrated assembly having bitlines spaced from one another by intervening voids. Insulative supports are over the bitlines. A conductive plate is supported by the insulative supports and is proximate the bitlines to drain excess charge from the bitlines. Some embodiments include a method of forming an integrated assembly. A stack is formed to have insulative material over bitline material. The stack is patterned into rails that extend along a first direction. The rails include the patterned bitline material as bitlines, and include the patterned insulative material as insulative supports over the bitlines. The rails are spaced from one another along a second direction, orthogonal to the first direction, by voids. Sacrificial material is formed within the voids. A conductive plate is formed over the insulative supports and the sacrificial material. The sacrificial material is removed from under the conductive plate to re-form the voids.