Multi-Die Semiconductor Package with Conductive Plate Interconnect
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Solution Overview
Problem
The integration of multiple semiconductor devices in miniaturized electronic devices poses challenges in achieving higher speed and lower transmission loss, requiring innovative packaging and assembling techniques to enhance electrical performance.
Innovation Solution
A semiconductor package manufacturing process involving a carrier with de-bonding layers, encapsulant formation, redistribution structures, and conductive pillars and plates to establish electrical connections between semiconductor dies, allowing for efficient integration and connection of multiple dies in a single package unit.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Adaptability or versatility
If multiple semiconductor devices are integrated in miniaturized electronic devices, then device functionality and electrical performance are improved, but manufacturing complexity and assembly difficulty increase
Solution Approach 1:
The patent divides the semiconductor manufacturing process into separate wafer-level packaging stages, where each die is independently packaged on the wafer before final assembly. This segmentation allows complex multi-device integration to be broken down into manageable, standardized units that can be manufactured efficiently at scale.
Solution Approach 2:
The patent transitions from traditional planar device layout to three-dimensional stacked architectures, where multiple semiconductor dies are vertically integrated using wafer-level packaging techniques. This dimensional change enables higher device functionality and electrical performance within miniaturized form factors while maintaining manufacturing efficiency through standardized vertical assembly processes.
2Productivity
If wafer level packaging techniques are used to integrate multiple semiconductor devices, then manufacturing efficiency is improved, but electrical performance and transmission loss challenges worsen
Solution Approach 1:
The patent performs preliminary electrical performance optimization during the wafer-level packaging process itself, rather than addressing transmission loss issues after final assembly. By pre-configuring interconnect structures and conducting preliminary testing at the wafer stage, the method ensures electrical performance requirements are met before devices are integrated into final products, thereby maintaining both manufacturing efficiency and electrical reliability.
3Reliability
If creative packaging and assembling techniques are developed to respond to miniaturization demands, then electrical performance is improved, but device complexity and manufacturing difficulty increase
Solution Approach 1:
The patent develops universal wafer-level packaging techniques that can accommodate multiple semiconductor devices with different electrical performance requirements using the same fundamental manufacturing processes. The standardized interconnect structures and packaging methods serve multiple functions across different device types, enabling improved electrical performance through creative packaging while avoiding the complexity of custom-designed packaging solutions for each device.
Data Source
AI summary
Semiconductor package includes a pair of dies, a redistribution structure, and a conductive plate. Dies of the pair of dies are disposed side by side. Each die includes a contact pad. Redistribution structure is disposed on the pair of dies, and electrically connects the pair of dies. Redistribution structure includes an innermost dielectric layer, an outermost dielectric layer, and a redistribution conductive layer. Innermost dielectric layer is closer to the pair of dies. Redistribution conductive layer extends between the innermost dielectric layer and the outermost dielectric layer. Outermost dielectric layer is furthest from the pair of dies. Conductive plate is electrically connected to the contact pads of the pair of dies. Conductive plate extends over the outermost dielectric layer of the redistribution structure and over the pair of dies. Vertical projection of the conductive plate falls on spans of the dies of the pair of dies.