Channelled Conductive Plate PCB Structure for Warpage Control
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Solution Overview
Problem
Existing high-performance computing systems face challenges in miniaturization, higher speed, and better electrical performance due to limitations in packaging and assembling techniques for integrated circuit components.
Innovation Solution
The use of a patterned conductive plate with channels, a core dielectric layer, and a metallization layer in the manufacturing method of a semiconductor device, which enhances structural rigidity, thermal dissipation, and electrical performance.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If conventional packaging and assembling techniques are used for integrated circuit components, then manufacturing simplicity is maintained, but miniaturization, speed, and electrical performance are limited
Solution Approach 1:
The circuit carrier is divided into multiple segments including a core layer with conductive plates and dielectric layers, build-up layers with conductive patterns, and asymmetric dielectric layers. This segmentation allows each layer to be optimized independently for miniaturization while maintaining overall manufacturing feasibility through standardized layering processes
Solution Approach 2:
The patent transitions from conventional planar PCB structures to a multi-dimensional layered architecture with conductive plates embedded within dielectric layers, conductive patterns formed on build-up layers, and asymmetric dielectric distributions. This dimensional evolution enables higher density interconnections and improved electrical performance without proportionally increasing manufacturing complexity
2Stability of the object's composition
If circuit carriers with high structural rigidity are used, then warpage during manufacturing is reduced, but manufacturing cost increases
Solution Approach 1:
The circuit carrier employs a composite structure combining conductive plates (e.g., copper, aluminum) embedded within dielectric layers, with build-up layers containing conductive patterns. This composite architecture provides high structural rigidity to prevent warpage during manufacturing while using cost-effective materials and standardized lamination processes to control manufacturing costs
Solution Approach 2:
The conductive plates are strategically positioned within the dielectric layers at locations where maximum structural support is needed to prevent warpage. The asymmetric dielectric layers are configured to provide localized rigidity enhancement in critical areas while maintaining cost efficiency by optimizing material distribution rather than uniformly increasing material thickness throughout the entire carrier
3Reliability
If asymmetric distribution of dielectric layers is implemented, then electrical inductance and resistance properties are improved, but manufacturing complexity increases
Solution Approach 1:
The asymmetric dielectric layers are configured with different thicknesses and material compositions in specific regions to optimize electrical inductance and resistance properties for high-speed signal transmission. This localized optimization allows improved electrical performance in critical signal paths while maintaining simpler symmetric configurations in non-critical areas, thereby controlling overall manufacturing complexity
Solution Approach 2:
The patent varies dielectric layer parameters including thickness, material composition, and positioning to achieve optimal electrical performance. By carefully controlling these parameters in the asymmetric configuration, the design achieves improved inductance and resistance characteristics while using standard lamination and patterning processes to manage manufacturing complexity
Data Source
AI summary
Circuit board includes conductive plate, core dielectric layer, metallization layer, first build-up stack, second build-up stack. Conductive plate has channels extending from top surface to bottom surface. Core dielectric layer extends on covering top surface and side surfaces of conductive plate. Metallization layer extends on core dielectric layer and within channels of conductive plate. Core dielectric layer insulates metallization layer from conductive plate. First build-up stack is disposed on top surface of conductive plate and includes conductive layers alternately stacked with dielectric layers. Conductive layers electrically connect to metallization layer. Second build-up stack is disposed on bottom surface of conductive plate. Second build-up stack includes bottommost dielectric layer and bottommost conductive layer. Bottommost dielectric layer covers bottom surface of conductive plate. Bottommost conductive layer is disposed on bottommost dielectric layer and electrically connects to metallization layer. First build-up stack includes more conductive and dielectric layers than second build-up stack.