Semiconductor Conductive Plate Layout for Thermal Interference Reduction
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Solution Overview
Problem
Conventional semiconductor devices face challenges in heat dissipation due to heat interference between semiconductor elements mounted on a common lead, leading to reduced thermal management efficiency.
Innovation Solution
The semiconductor device configuration includes a first conductive plate, a second conductive plate, and a third conductive plate, with semiconductor elements arranged in an inverted posture in the thickness direction, allowing heat from each element to be dispersed and released to separate plates, enhancing heat dissipation and reducing inductance.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Ease of manufacture
If two semiconductor elements are mounted on a single lead, then the device structure is simplified and manufacturing is easier, but heat dissipation performance deteriorates due to heat interference between elements
Solution Approach 1:
The patent divides the heat dissipation function by providing multiple separate leads (first lead and second lead) instead of using a single lead. Each semiconductor element is mounted on a separate lead, allowing heat from each element to be dissipated independently through its own lead to the heat dissipation plate, thereby eliminating heat interference between elements while maintaining manufacturing simplicity.
2Device complexity
If multiple semiconductor elements share a common lead, then device complexity is reduced, but thermal management efficiency deteriorates
Solution Approach 1:
The patent segments the thermal management system by providing separate heat dissipation paths for each semiconductor element through individual leads. The first semiconductor element is mounted on the first lead and the second semiconductor element is mounted on the second lead, with both leads connected to the heat dissipation plate. This segmentation allows independent heat dissipation for each element, improving thermal management efficiency while maintaining relatively simple device structure.
3Temperature
If semiconductor elements are mounted on separate leads, then heat dissipation performance is improved by reducing heat interference, but device complexity increases
Solution Approach 1:
The patent merges multiple leads (first lead and second lead) at a common heat dissipation plate, allowing them to share the thermal management function. This merging approach enables separate heat dissipation paths for each semiconductor element while consolidating the heat dissipation function at a single location, thereby improving heat dissipation performance without proportionally increasing device complexity.
Solution Approach 2:
The heat dissipation plate serves as a universal component that handles heat dissipation for multiple semiconductor elements simultaneously. By making the heat dissipation plate multi-functional (serving both the first and second semiconductor elements), the patent achieves separate heat dissipation paths for each element while using a shared heat dissipation resource, thus improving thermal performance without linearly increasing device complexity.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This configuration improves heat dissipation properties and reduces inductance by allowing efficient heat transfer and release to separate conductive plates, thereby enhancing the thermal management of the semiconductor device.
Implementation Method 1
heat from each element to be dispersed and released to separate plates, enhancing heat dissipation
Data Source
AI summary
A semiconductor device includes: a first conductive plate and a second conductive plate spaced apart from each other in a direction x; a third conductive plate facing the first and second conductive plates in a direction z; a first semiconductor element arranged between the first conductive plate and the third conductive plate; a second semiconductor element arranged between the second conductive plate and the third conductive plate; a positive input terminal electrically connected to the first conductive plate; a negative input terminal electrically connected to the second conductive plate; an output terminal electrically connected to the third conductive plate; and a sealing resin covering at least the first and second semiconductor elements.