Stacked Semiconductor Package Using Conductive Posts and Dummy Solder
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Solution Overview
Problem
Current semiconductor packaging technologies, such as through-silicon via (TSV) process technology, face challenges in reducing size and cost while maintaining electrical characteristics, especially for high-frequency signal processing applications.
Innovation Solution
A semiconductor package design featuring a first semiconductor chip mounted on a substrate with a conductive post, a second semiconductor chip stacked on the first, and a mold layer covering both, utilizing dummy and signal solder terminals for structural support and electrical connectivity, which allows for improved structural stability and reduced size without increasing complexity or cost.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If TSV process technology is used to stack memory chips, then electrical characteristics are improved, but device complexity and manufacturing cost increase
Solution Approach 1:
The patent extracts the essential function of TSV (vertical electrical connection) and implements it through a simplified structure: conductive posts are formed directly on the substrate without requiring through-silicon vias, and dummy solder terminals are used to provide mechanical support without electrical connection, separating the electrical and mechanical support functions into distinct elements
Solution Approach 2:
The substrate serves multiple functions: it provides the base mounting surface for chips, contains conductive posts for vertical electrical connections, and supports dummy solder terminals for mechanical reinforcement. This multi-functionality eliminates the need for complex TSV structures while maintaining electrical performance
2Reliability
If TSV process technology is used to stack memory chips, then electrical characteristics are improved, but manufacturing cost increases
Solution Approach 1:
The patent uses dummy solder terminals made of solder material that provides mechanical support but is not electrically connected to the chip circuits. These dummy terminals are simpler to manufacture than functional TSV structures and can be produced using standard reflow processes, reducing manufacturing cost while maintaining electrical performance through separate signal solder terminals
3Volume of moving object
If multiple memory chips are stacked to reduce size, then volume is reduced, but structural stability becomes challenging
Solution Approach 1:
The patent places dummy solder terminals between the first and second chips to provide counterbalancing mechanical support. These dummy terminals act as reinforcement elements that counteract the stress and potential misalignment forces in the stacked configuration, enhancing structural stability while maintaining compact volume
Solution Approach 2:
The dummy solder terminals are positioned in advance during the stacking process to provide pre-compression and alignment support between chips. This beforehand cushioning prevents structural issues during operation by ensuring proper mechanical coupling before electrical signals are transmitted
4Volume of moving object
If chip size is reduced to minimize package dimensions, then volume is reduced, but electrical connection path length becomes critical
Solution Approach 1:
The patent transitions from horizontal chip arrangement to vertical stacking with conductive posts extending upward from the substrate. This dimensional change allows electrical connections to be made in the vertical direction, shortening the connection path length between chips while reducing the horizontal footprint of the package
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
The design enhances structural stability and electrical characteristics by reducing the size of the semiconductor package, shortening the electric connection path, and maintaining robust support for the second semiconductor chip, thereby addressing the limitations of existing TSV process technologies.
Implementation Method 1
performing a reflow process on the first and second solder terminals to respectively form a signal solder terminal connecting the signal pad to the conductive post and a dummy solder terminal connecting the dummy pad to a top surface of the first semiconductor chip
Data Source
AI summary
A semiconductor package includes a first semiconductor chip mounted on a substrate, a first conductive post disposed on the substrate and spaced apart from the first semiconductor chip, a second semiconductor chip disposed on the first semiconductor chip and the first conductive post, and a mold layer on the substrate that covers the first and second semiconductor chips and the first conductive post. The second semiconductor chip is supported on the first semiconductor chip by a first dummy solder terminal provided between the first and second semiconductor chips, and is coupled to the first conductive post by a first signal solder terminal provided between the first conductive post and the second semiconductor chip. The first dummy solder terminal is in direct contact with a top surface of the first semiconductor chip, and is electrically disconnected from the second semiconductor chip.