Conductive Post Ring Structure for NAND Etch Protection
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Solution Overview
Problem
There is a need for improved methods of forming integrated memory devices, particularly NAND memory devices, to enhance the formation of conductive posts and protect lower regions during etching processes.
Innovation Solution
The use of insulative rings laterally surrounding lower regions of conductive posts during etching processes, utilizing materials such as carbon-doped silicon oxide or silicon nitride, to protect the posts and enhance the formation of integrated assemblies.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If conventional etching processes are used without protective structures, then the etching process is simpler and faster, but the conductive posts cannot be protected from damage during etching
Solution Approach 1:
The patent applies preliminary action by forming insulative rings around the lower regions of conductive posts before the etching process. These rings are prepared in advance as protective structures that prevent etchant damage to the posts during subsequent processing steps.
Solution Approach 2:
The insulative rings serve as intermediary protective structures between the etchant and the conductive posts. They act as a mediator that allows the etching process to proceed while preventing direct contact between the harmful etchant and the vulnerable conductive post regions.
2Manufacturing precision
If insulative rings are added to protect conductive posts, then protection during etching is improved, but the manufacturing process becomes more complex
Solution Approach 1:
The insulative rings are formed preliminarily before the conductive posts are created, establishing precise boundaries and protection zones in advance. This preliminary structuring enables precise post formation while maintaining manufacturing feasibility through sequential processing steps.
Data Source
AI summary
Some embodiments include an integrated assembly having a first memory region, a second memory region offset from the first memory region, and an intermediate region between the first and second memory regions. Channel-material-pillars are arranged within the first and second memory regions. Conductive posts are arranged within the intermediate region. A panel extends across the first memory region, the intermediate region and the second memory region. The panel is between a first memory-block-region and a second memory-block-region. Doped-semiconductor-material is within the first memory region, the second memory region and the intermediate region, and is directly adjacent the panel. The doped-semiconductor-material is at least part of conductive source structures within the first and second memory regions. Insulative rings surround lower regions of the conductive posts and are between the conductive posts and the doped-semiconductor-material. Some embodiments include methods of forming integrated assemblies.