Conductive Post Stacked Semiconductor Package for Low-Loss Power Delivery
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Solution Overview
Problem
Existing semiconductor packages face challenges in increasing reliability and integration density while miniaturizing the packages to support the development of advanced electronics.
Innovation Solution
A semiconductor package design featuring a stacked semiconductor chip configuration on a conductive post, with a redistribution substrate and multiple bumps and interconnection structures to enhance electrical connectivity and thermal management.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Quantity of substance
If a stacked semiconductor chip configuration is used, then integration density is improved, but voltage loss increases
Solution Approach 1:
The voltage supply path is segmented into multiple independent conductive posts distributed across the substrate, with each post serving specific upper semiconductor chips. This segmentation reduces the current carrying distance for each post, thereby reducing voltage loss while maintaining high integration density through the stacked configuration.
Solution Approach 2:
The patent transitions from a planar two-dimensional layout to a three-dimensional stacked configuration by vertically arranging upper semiconductor chips above lower semiconductor chips and conductive posts. This dimensional change enables shorter electrical connection paths and reduced voltage loss while achieving higher integration density in the vertical direction.
2Quantity of substance
If a stacked semiconductor chip configuration is used, then integration density is improved, but heat dissipation becomes more difficult
Solution Approach 1:
Heat dissipation is segmented through multiple independent heat dissipation paths: each conductive post serves as a thermal conduction path from upper semiconductor chips to the substrate, and lateral heat dissipation paths are provided through the substrate structure. This segmentation enables effective heat removal while maintaining the stacked high-density configuration.
Solution Approach 2:
The conductive posts serve as intermediary thermal conduction paths between the upper semiconductor chips and the substrate. These posts facilitate heat transfer from the upper chips through the posts to the substrate, which then dissipates heat laterally, providing an effective thermal management pathway in the stacked configuration.
3Reliability
If conductive posts are laterally spaced apart from lower semiconductor chip, then reliability is improved, but device complexity increases
Solution Approach 1:
The conductive posts are designed to perform multiple functions simultaneously: they provide voltage supply to upper semiconductor chips, serve as thermal conduction paths for heat dissipation, and act as structural support elements. This multi-functionality reduces the need for separate components, thereby limiting the increase in device complexity while achieving improved reliability.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
The solution improves the reliability and integration density of semiconductor packages by providing a stable voltage supply to the upper semiconductor chip, reducing voltage loss, and effectively dissipating heat generated by the upper chip.
Implementation Method 1
the conductive posts are configured to supply a voltage to the upper semiconductor chip
Implementation Method 2
each of the plurality of first bumps includes a first pillar pattern and a first solder pattern disposed on the first pillar pattern
Data Source
AI summary
A semiconductor package includes a first substrate, a lower semiconductor chip on the first substrate, a conductive post disposed on the first substrate, and including at least a portion laterally spaced apart from the lower semiconductor chip, an upper semiconductor chip on the lower semiconductor chip and the conductive post, and a plurality of first bumps disposed between the conductive post and the upper semiconductor chip, wherein each of the plurality of first bumps includes a first pillar pattern and a first solder pattern disposed on the first pillar pattern.