Conductive Post Surface Treatment for Power Module Thermal Stress
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Solution Overview
Problem
In power semiconductor modules, excessive bonding material can rise due to capillary phenomena during reflow, causing thermal stress between copper conductive posts and solder, leading to semiconductor chip damage, especially in wide band gap chips operating at higher temperatures.
Innovation Solution
The conductive post surface is engineered with a plated layer of higher wettability at the leading end and lower wettability at the central portion to control bonding material distribution, limiting its rise and reducing thermal stress through selective wetting during reflow.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Strength
If the amount of bonding material is increased to ensure adequate electrical and mechanical connection, then the bonding strength is improved, but the bonding material rises to the central portion of the conductive post due to capillary phenomenon, causing thermal stress and potential chip damage
Solution Approach 1:
The conductive post is designed with different surface properties at different locations: the leading end has a surface treatment (such as plating or roughening) that promotes bonding material adhesion, while the central portion has a surface treatment that prevents capillary rise. This local differentiation allows adequate bonding strength at the interface without allowing bonding material to rise into the central portion, thereby preventing thermal stress and chip damage.
2Stress or pressure
If the linear expansion coefficient difference between conductive post and bonding material is reduced, then thermal stress is minimized, but material selection becomes more restricted
Solution Approach 1:
Instead of selecting materials based on matching linear expansion coefficients, the invention changes the approach by treating the surface properties of the conductive post. By applying surface treatments (plating, roughening, or coating) to the leading end and central portion differently, the invention controls bonding material behavior without being constrained by material expansion coefficient matching, thus maintaining material selection flexibility while minimizing thermal stress.
3Strength
If the wettability of the conductive post surface is increased to improve bonding material adhesion, then the bonding strength is improved, but the bonding material rises more easily along the conductive post due to capillary action
Solution Approach 1:
The conductive post surface is treated differently at different locations: the leading end receives a surface treatment that enhances wettability and adhesion for strong bonding, while the central portion receives a surface treatment that reduces wettability to prevent capillary rise. This local differentiation allows the bonding material to adhere strongly at the interface without rising along the conductive post, thereby achieving both strong bonding and controlled rise height.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach suppresses thermal stress and enhances reliability by controlling bonding material placement, mitigating the effects of differing linear expansion coefficients between the conductive post and bonding material.
Implementation Method 1
excessive bonding material can rise due to capillary phenomena during reflow
Implementation Method 2
The conductive post surface is engineered with a plated layer of higher wettability at the leading end and lower wettability at the central portion to control bonding material distribution
Implementation Method 3
the linear expansion coefficient of the conductive post 108 is about 16.5×10−6 (1/° C.). When the bonding material 107 is solder, the linear expansion coefficient of the bonding material 107 is in the range of about 22.0×10−6 (1/° C.) to 24.0×10−6 (1/° C.). When the semiconductor chip 106 operates to generate heat in the state illustrated in FIG. 6(a) and an ambient temperature increases, thermal stress is generated
Data Source
AI summary
The semiconductor device includes an insulating substrate including an insulating plate and a circuit plate; a semiconductor chip having a front surface formed with an electrode and a rear surface fixed to the circuit plate; a printed circuit board including a metal layer, and facing the insulating substrate; a conductive bonding material disposed on the electrode; and a conductive post having a leading end portion electrically and mechanically connected to the electrode through the bonding material, a base portion electrically and mechanically connected to the metal layer, and a central portion. In the conductive post, a wetting angle of a surface of the leading end portion with respect to the molten bonding material is less than the wetting angle of a surface of the central portion.