Conductive Posts for Thin Electronic Packages
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Solution Overview
Problem
Conventional 3D IC chip stacking technologies face challenges in miniaturization due to thick packaging substrates and high fabrication costs, with TSVs requiring extensive processing and causing silicon interposer warping during encapsulation.
Innovation Solution
The solution involves forming conductive posts directly on a circuit structure, encapsulating them with an insulating layer, and using these posts as a signal transmission medium, eliminating the need for a silicon interposer and allowing for varied aspect ratios, thus simplifying the fabrication process and reducing thickness and cost.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If TSVs are used to achieve signal transmission between semiconductor chip and packaging substrate, then electrical connection is established, but fabrication complexity and cost increase due to extensive processing requirements
Solution Approach 1:
The patent extracts the TSV structure from the silicon interposer and relocates it to the packaging substrate. This separation eliminates the need for complex TSV fabrication in the interposer while maintaining the essential signal transmission function through alternative structures like through-hole conductors or surface-mounted conductive elements.
Solution Approach 2:
The patent employs simpler, less expensive conductor structures (such as through-hole plating or surface conductive traces)替代 the complex TSV structures. These alternative conductors achieve the same electrical connection function with reduced fabrication complexity and lower material costs.
2Reliability
If silicon interposer with TSVs is used for signal transmission, then electrical connection is achieved, but fabrication time and chemical consumption increase
Solution Approach 1:
The patent removes the TSV fabrication process from the silicon interposer manufacturing sequence and integrates conductor formation into the packaging substrate fabrication process. This reorganization eliminates time-consuming steps like deep hole drilling, lining, and plating in the interposer, reducing overall fabrication time.
Solution Approach 2:
The patent combines the conductor formation process with the packaging substrate manufacturing process. By integrating these functions into a single fabrication sequence, the patent eliminates redundant processing steps and reduces total fabrication time and chemical consumption.
3Strength
If packaging substrate with core layer containing glass fiber is used, then structural support is provided, but package thickness increases hindering miniaturization
Solution Approach 1:
The patent employs thin-film conductor structures and streamlined substrate designs that provide sufficient structural support with minimal thickness. By using deposited metal layers and optimized substrate compositions, the patent achieves mechanical strength without the bulk added by traditional glass fiber core layers.
Solution Approach 2:
The patent uses composite material structures combining organic substrates with embedded conductive layers. This approach provides the necessary structural support and electrical functionality while maintaining thin profile, enabling package miniaturization without sacrificing mechanical integrity.
4Reliability
If multiple heating processes are applied during encapsulant formation, then encapsulation is achieved, but silicon interposer warping occurs due to temperature variation
Solution Approach 1:
The patent removes the silicon interposer from the encapsulation process by placing conductors directly on the packaging substrate. This eliminates the interposer from exposure to high-temperature encapsulation processes, preventing warping while maintaining the encapsulation function through alternative structures.
Solution Approach 2:
The patent creates functional equivalents of the TSV-conductor system using surface-mounted conductive elements and through-hole plating. These alternative structures achieve the same electrical connection and signal transmission functions without requiring a thick silicon interposer that would be susceptible to warping during heating.
Data Source
AI summary
An electronic package is provided, which includes: a circuit structure having opposite first and second surfaces; a metal layer formed on the first surface of the circuit structure; an electronic element disposed on the metal layer; an encapsulant encapsulating the electronic element; a plurality of conductive posts disposed on the second surface of the circuit structure; and an insulating layer encapsulating the conductive posts. The conductive posts of various sizes can be fabricated according to different aspect ratio requirements so as to make end products lighter, thinner, shorter and smaller. The disclosure further provides a method for fabricating the electronic package.