Conductive Posts for High Aspect Ratio Vias in Semiconductor Packaging
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Solution Overview
Problem
Current semiconductor packaging technologies face challenges in achieving optimal RF performance and mechanical strength due to limitations in dielectric layer thickness and via aspect ratio, which affect capacitive coupling and manufacturing tolerances, especially when trying to accommodate both small and large metal structures for power and ground connections.
Innovation Solution
The use of conductive posts on semiconductor pads allows for the formation of vias with reduced depth, maintaining a constant aspect ratio and enabling the fabrication of both small and large vias, thereby improving RF performance and manufacturability by reducing capacitive coupling and mechanical stress.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If the dielectric layer thickness is reduced to improve RF performance by limiting capacitive coupling, then RF performance is improved, but the via aspect ratio increases making manufacturing difficult
Solution Approach 1:
The via formation process is segmented into two stages: first forming a conductive post at the pad location, then forming the via hole down to the post. This segmentation allows the via hole depth to be reduced while maintaining the overall connection length, thereby reducing the aspect ratio of the via hole itself while still achieving the desired electrical connection through the dielectric layer.
Solution Approach 2:
A conductive post is formed at the pad location before forming the via hole. This preliminary action provides a conductive base that extends partway through the dielectric layer, allowing the subsequent via hole to be shallower and easier to manufacture while maintaining the necessary electrical connection path.
2Strength
If the dielectric layer thickness is increased to improve mechanical strength, then mechanical strength is improved, but capacitive coupling increases degrading RF performance
Solution Approach 1:
The conductive post provides localized electrical connection at critical pad locations, allowing the dielectric layer to be thicker for mechanical strength while maintaining good RF performance. The post creates a direct conductive path that reduces the effective coupling distance locally, compensating for the increased overall dielectric thickness.
3Reliability
If small vias are used on small pads to reduce capacitive coupling, then RF performance is improved, but the via aspect ratio becomes too high for manufacturing
Solution Approach 1:
The electrical connection is segmented into two parts: the conductive post that extends vertically from the pad, and the via hole that connects to the post. This allows the via hole to be shallower and easier to manufacture, while the post provides the necessary vertical connection path, effectively reducing the via hole aspect ratio for small pads.
Solution Approach 2:
The conductive post acts as an intermediary structure between the pad and the via hole. It provides a conductive bridge that reduces the depth requirement of the via hole, making small via fabrication feasible while maintaining low capacitive coupling through the reduced via hole depth.
4Reliability
If large vias are used on power/ground connections to reduce mechanical stress, then mechanical reliability is improved, but the via depth must be increased affecting aspect ratio
Solution Approach 1:
The connection structure is segmented into a conductive post that provides mechanical strength and a shallower via hole that is easier to manufacture. The post serves as a robust mechanical anchor point, allowing the via hole to be shorter and have a lower aspect ratio while still achieving the necessary mechanical and electrical connection.
Solution Approach 2:
The conductive post is formed in advance to provide a mechanical foundation. This preliminary structure allows subsequent via holes to be formed with reduced depth requirements, as the post already provides part of the necessary connection path and mechanical support.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach enhances RF performance and mechanical reliability by allowing for smaller vias on small pads and larger vias on power/ground connections, while maintaining a constant aspect ratio, thus improving the overall packaging efficiency and reducing the risk of catastrophic failures.
Implementation Method 1
The dielectric layer also defines a gap or distance between the functional metal structures of the die and the redistribution layers that connect to the board. This gap improves electrical performance, by limiting capacitive coupling between the RDL and the die surface.
Implementation Method 2
filling the formed holes with a conductive material
Data Source
AI summary
Conductive paths through a dielectric are described that have a high aspect ratio for semiconductor devices. In one example, a semiconductor device package has a semiconductor substrate having circuitry formed on the substrate. A plurality of conductive connection pads are on the semiconductor substrate to connect to the circuitry. A post is on each of a subset of the connection pads, the posts being formed of a conductive material. A dielectric layer is over the semiconductor substrate including over the connection pads and the posts. Filled vias are over each connection pad that is not of the subset and over each post of the subset of the connection pads and a connector is over each filled via.