Conductive Rail Layout for Dense Semiconductor Power Routing
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Solution Overview
Problem
The increasing complexity of interconnect routing in compact integrated circuits due to higher transistor counts and the significant area occupancy by metal line routings for power rails, which hinders the miniaturization of semiconductor devices.
Innovation Solution
A conductive rail structure is introduced that connects transistors to power or ground levels laterally between adjacent fin structures on a substrate, reducing the need for metal line routing at the interconnect level and thereby minimizing the area occupied by power rails.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If transistor count is increased to achieve higher storage capacity and processing performance, then device functionality is improved, but interconnect routing complexity increases
Solution Approach 1:
The power distribution network is segmented into multiple independent conductive rails positioned at different vertical levels. Each rail can be independently routed and connected to transistors, allowing power delivery without requiring complex lateral interconnect routing between transistors. This segmentation resolves the routing complexity issue while maintaining high transistor density.
Solution Approach 2:
The patent transitions from two-dimensional lateral power routing to three-dimensional vertical power distribution by positioning conductive rails above and below the transistor plane. This dimensional change allows power rails to pass through or adjacent to transistor regions without occupying lateral layout area, thereby reducing interconnect routing complexity while supporting high transistor counts.
2Use of energy by moving object
If metal line routing is used for power rails, then power delivery is achieved, but significant layout area is occupied
Solution Approach 1:
Power rails are positioned in the vertical dimension above and below the transistor active area rather than occupying lateral layout space. Multiple conductive rails at different heights deliver power through the vertical stack, enabling efficient power distribution while minimizing the horizontal footprint and maximizing transistor density.
Solution Approach 2:
The conductive rails are nested within the vertical stack structure, with insulation layers and barrier structures integrated between the rails and transistors. This nesting allows power delivery infrastructure to be embedded within the device cross-section without increasing lateral dimensions, thereby reducing overall layout area while maintaining power delivery capability.
Data Source
AI summary
The present disclosure describes a semiconductor structure and a method for forming the same. The semiconductor structure can include a substrate, a first vertical structure and a second vertical structure formed over the substrate, and a conductive rail structure between the first and second vertical structures. A top surface of the conductive rail structure can be substantially coplanar with top surfaces of the first and the second vertical structures.