Conductive Sheet for Semiconductor Dynamic Testing
Find Innovative SolutionsGenerate Solutions
Solution Overview
Problem
Dynamic characteristic tests for vertical semiconductor devices often result in cracks that can propagate radially, damaging adjacent non-defective chips and reducing inspection efficiency, as these tests cannot be continuously performed on the same stage without moving semiconductor chips after dicing.
Innovation Solution
A method involving a conductive sheet fixed to the semiconductor substrate, allowing division into chips and continuous dynamic testing on a support stage, where the sheet ensures electrical conductivity and prevents fissure propagation by stabilizing high current switching tests.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If dynamic characteristic test is performed on vertical semiconductor devices in wafer state, then high current switching test can be conducted, but fissures grow in radial pattern from cracks and damage adjacent nondefective devices
Solution Approach 1:
The semiconductor wafer is divided into individual chips, and testing is performed on each chip separately rather than on the entire wafer. This segmentation prevents radial fissure propagation from affecting adjacent devices, as each chip is tested independently after dicing.
Solution Approach 2:
The semiconductor wafer is diced into individual chips before performing the dynamic characteristic test. This preliminary action of dividing the wafer eliminates the risk of fissure propagation between adjacent devices during high current switching testing.
2Reliability
If semiconductor chips are moved to prober using chip handler after dicing for dynamic characteristic test, then individual chip testing can be performed, but continuous test on same stage cannot be achieved and inspection efficiency is reduced
Solution Approach 1:
The support stage is designed to maintain consistent positioning and electrical connectivity for multiple chips simultaneously. By keeping chips on the same stage throughout the testing process without movement to separate probers, the system achieves both continuous testing capability and consistent test conditions.
Solution Approach 2:
Multiple chip testing functions are combined into a single support stage system. The stage can hold and test multiple chips simultaneously or sequentially without requiring chip handlers to move chips between different testing stations, thereby improving inspection efficiency.
3Reliability
If semiconductor chips are tested individually after dicing, then fissure propagation to adjacent chips is prevented, but continuous testing on same stage is not possible and productivity decreases
Solution Approach 1:
The wafer is divided into separate chips to prevent fissure propagation, while the support stage is designed to accommodate multiple individual chips simultaneously. This allows independent testing of each chip while maintaining high throughput through parallel or sequential testing on the same stage.
Solution Approach 2:
The support stage is designed with universal functionality to handle multiple chips of the same type simultaneously. It can perform continuous testing on multiple chips without requiring chip handlers, achieving both device integrity protection and high testing productivity through multi-chip capability.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This method enhances inspection efficiency and yield by preventing fissure propagation and allowing continuous testing of semiconductor chips on the same stage, improving the productivity of semiconductor modules.
Implementation Method 1
fixing a sheet having electrical conductivity to a main surface of a semiconductor substrate
Implementation Method 2
the sheet ensures electrical conductivity and prevents fissure propagation by stabilizing high current switching tests
Data Source
AI summary
A yield and productivity of a semiconductor module are improved. A sheet having electrical conductivity is fixed to a main surface of a semiconductor substrate on which a plurality of semiconductor devices having a surface structure and a rear surface electrode are arranged. The semiconductor substrate is divided into semiconductor chips on a first support stage in the state where the sheet is fixed to its main surface. The plurality of divided semiconductor chips are mounted on a second support stage via the sheet and further, the plurality of mounted semiconductor chips are continuously subjected to a dynamic characteristic test on the second support stage. The proposed semiconductor device evaluation method permits a fissure growing and propagating from a crack occurring in the dynamic characteristic test of the vertical semiconductor devices to be suppressed, and the yield and productivity of the semiconductor module to be improved.