Conductive Spacers Extend Floating Gates
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Solution Overview
Problem
Existing methods for improving the floating gate to control gate coupling ratio in non-volatile memory cells, such as those used in flash memories, face challenges in reducing cell size while maintaining reliability and preventing fence leakage, as they either result in rough surfaces, nitride residues, or complex processing steps that compromise capacitance and lithographic limitations.
Innovation Solution
A method involving the formation of conductive spacers extending the floating gate, allowing for increased overlap with the control gate without increasing cell size, using polysilicon spacers that extend vertically over the floating gate sidewalls and into recesses in the isolation zones, enhancing the coupling ratio and preventing fence leakage.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If the floating gate dimensions are increased to improve coupling ratio, then the capacitance between FG and CG increases, but the cell size increases and device density decreases
Solution Approach 1:
The patent extends the floating gate in the vertical dimension by adding conductive spacers that protrude from the sidewalls of the floating gate. This vertical extension increases the overlap area with the control gate without increasing the horizontal footprint of the cell, thereby improving the coupling ratio while maintaining device density.
2Reliability
If conventional slit etching methods are used to isolate floating gates, then isolation is achieved, but fence leakage occurs between adjacent floating gates
Solution Approach 1:
The patent introduces an intermediary structure - the conductive spacer extension - that protrudes from the floating gate sidewalls into the isolation region. This extension effectively extends the floating gate into the isolation zone, creating an earlier barrier that prevents charge leakage between adjacent floating gates through the fence region.
3Manufacturing precision
If nitride spacers are used to form small slits, then lithographic limitations are overcome, but nitride residues and rough surfaces are created that reduce IPD reliability
Solution Approach 1:
The patent changes the material parameter from nitride to polysilicon for the spacer formation. This material substitution allows for the formation of sharp, clean interfaces without the residue problems associated with nitride etching, thereby maintaining manufacturing precision while improving IPD reliability.
Solution Approach 2:
The patent uses a sacrificial oxide layer that is deposited and then selectively removed to define the spacer region. This disposable oxide layer enables precise pattern transfer without leaving harmful residues, as it is completely removed after serving its patterning function.
4Productivity
If the space between floating gates is reduced to increase density, then device density improves, but the coupling ratio decreases due to reduced overlap area
Solution Approach 1:
By extending the floating gate vertically with conductive spacers, the patent compensates for the reduced horizontal overlap area that results from tighter spacing. The vertical extension maintains sufficient coupling capacitance even when floating gates are closely spaced, enabling high density without sacrificing coupling ratio.
Data Source
AI summary
A method for manufacturing on a substrate a semiconductor device with a floating-gate and a control-gate. The method includes the steps of first forming an isolation zone in the substrate, and thereafter forming the floating gate on the substrate. The method further includes extending the floating gate using spacers, and then forming the control gate over the floating gate and the spacers.