Conductive Spline for Metal Gate Debiasing
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Solution Overview
Problem
Integrated circuits with metal gates less than 30 nanometers in width experience high electrical resistance due to debiasing issues, particularly in high-frequency components and local interconnects, making it challenging to design circuits that avoid these problems.
Innovation Solution
A conductive spline is formed on the metal gate, extending over the isolation dielectric layer for a length at least four times the width of the metal gate, which includes an adhesion layer, a barrier layer, and a fill metal, reducing debiasing by providing additional conductivity and enabling efficient routing of interconnects.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If metal gates with widths less than 30 nanometers are used, then the integrated circuit can achieve higher integration density, but the electrical resistance per unit length becomes undesirably high due to debiasing issues
Solution Approach 1:
A conductive spline is introduced as an intermediary element between the metal gate and the isolation dielectric layer. This spline extends along the metal gate for a length at least four times the width of the metal gate, providing an additional conductive path that compensates for the high resistance of narrow metal gates and reduces debiasing effects
Solution Approach 2:
The conductive spline extends in the lateral dimension along the metal gate, creating a three-dimensional conductive structure. By extending the spline length to at least four times the metal gate width, the solution adds a spatial dimension to the conductive path, effectively reducing resistance without increasing the vertical profile
2Reliability
If the conductive spline extends for a length at least four times the width of the metal gate, then debiasing is effectively reduced, but the device complexity increases
Solution Approach 1:
The conductive spline uses the same material composition (adhesion layer, barrier layer, and fill metal) as the metal gate itself. By maintaining consistent material parameters across different structures, the patent reduces fabrication complexity while achieving the desired electrical performance improvement
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
The conductive spline effectively reduces signal debiasing along the metal gates, improving the electrical performance and layout efficiency of integrated circuits by maintaining signal integrity and allowing for smaller circuit sizes.
Implementation Method 1
A conductive spline is formed on the metal gate, extending on the metal gate over at least a portion of the isolation dielectric layer, and extending on the metal gate for a length at least four times a width of the metal gate
Data Source
AI summary
An integrated circuit may include a metal gate which extends over an active area and onto an isolation dielectric layer. A conductive spline is formed on the metal gate, extending on the metal gate over at least a portion of the isolation dielectric layer, and extending on the metal gate for a length at least four times a width of the metal gate.