Conductive THV and RDL for RDL-to-RDL Bonding
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Solution Overview
Problem
Current semiconductor manufacturing processes face challenges in efficiently and cost-effectively interconnecting semiconductor die, particularly due to issues with conductive vias and bumps leading to defects and reduced reliability in vertical interconnects.
Innovation Solution
A method involving the formation of conductive vias and redistribution layers on both sides of a semiconductor die, using a carrier with an encapsulant and multiple conductive layers to facilitate efficient electrical connection without the need for interconnect bumps, thereby enhancing reliability and reducing costs.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If conductive vias are filled completely with electrically conductive material, then electrical connectivity is achieved, but the process becomes time consuming and costly
Solution Approach 1:
The patent extracts the unnecessary portion of the via (the center of high aspect ratio vias) and leaves it empty, filling only the sidewalls with conductive material. This extraction approach maintains electrical connectivity along the via path while dramatically reducing the amount of conductive material required and the time needed for the filling process.
Solution Approach 2:
Instead of completely filling the via (excessive action), the patent applies partial filling by depositing conductive material only on the sidewalls. This partial action is sufficient to achieve the necessary electrical connectivity function while avoiding the drawbacks of complete filling.
2Reliability
If high aspect ratio vias are filled with conductive material, then vertical interconnect is achieved, but voids form causing defects
Solution Approach 1:
The patent removes the problematic center portion of high aspect ratio vias from the filling process, extracting only the sidewalls for conductive material deposition. This eliminates the void formation issue that plagues complete filling of high aspect ratio vias while maintaining the necessary electrical connection.
Solution Approach 2:
The patent applies different quality requirements to different parts of the via: the sidewalls receive conformal conductive material deposition for electrical connectivity, while the center remains empty. This local differentiation in material distribution solves the void formation problem while maintaining interconnect reliability.
3Area of stationary object
If contact area between THV and bumps is kept small, then device footprint is reduced, but interconnect becomes prone to breakage
Solution Approach 1:
The patent performs preliminary action by forming a large contact area between the via and contact pad during the same deposition process, before any bonding or interconnection steps. This preliminary establishment of a large bonding area ensures strong mechanical and electrical connection while maintaining a compact overall device footprint.
Solution Approach 2:
The patent transitions from a point-contact or small-area bump connection to a distributed sidewall contact along the via height. This dimensional change from a localized contact to an extended contact area along the via provides both mechanical strength and electrical connectivity without increasing the horizontal footprint.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach enables cost-effective and reliable electrical interconnection of semiconductor die, reducing defects and improving the reliability of vertical interconnects by increasing the contact area and eliminating the need for interconnect bumps, thus enhancing the performance and efficiency of semiconductor devices.
Implementation Method 1
depositing an encapsulant over the carrier around a peripheral region of the semiconductor die
Implementation Method 2
conformally applying a first conductive layer over a sidewall of the vias to form conductive vias
Implementation Method 3
forming a third conductive layer over a second surface of the semiconductor die opposite the first surface of the semiconductor die. The third conductive layer is electrically connected to the conductive vias.
Data Source
AI summary
A semiconductor device has a plurality of semiconductor die mounted to a carrier. An encapsulant is deposited over the carrier around a peripheral region of the semiconductor die. A plurality of vias is formed through the encapsulant. A first conductive layer is conformally applied over a sidewall of the vias to form conductive vias. A second conductive layer is formed over a first surface of the semiconductor die between the conductive vias and contact pads of the semiconductor die. The first and second conductive layers can be formed during the same manufacturing process. A third conductive layer is formed over a second surface of the semiconductor die opposite the first surface of the semiconductor die. The third conductive layer is electrically connected to the conductive vias. A plurality of semiconductor die is stacked and electrically connected through the conductive vias and second and third conductive layers.