Conductive Tracks in Mold Compound via Electroless Plating

Resolve Bottlenecks,
Find Innovative Solutions
Generate Solutions

Solution Overview

Problem

Existing semiconductor packaging techniques face challenges in space efficiency and cooling, particularly with chip-stacking solutions where direct electrical interconnection between stacked devices is complex and costly, often requiring an interposer that increases thickness and complexity.

Innovation Solution

A method of forming conductive tracks within the mold compound of packaged semiconductor devices using a multi-layer exterior compound with laser structuring and electroless plating, allowing for direct electrical connections between leads without the need for an interposer, enabling compact designs with independent cooling for each chip.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Area of stationary object

If chip-stacking solutions are used to improve space efficiency, then the area utilization is improved, but the device complexity and cooling capability deteriorate

Engineering Contradiction:
Improvearea utilizationVSAvoiddevice complexity
Core Design Contradiction:
Area of stationary objectVSDevice complexity

Solution Approach 1:

The patent segments the package into multiple independent stacked devices, each with its own lead frame and semiconductor die. This allows space-efficient vertical arrangement while maintaining independent electrical and thermal pathways for each segment, avoiding the complexity of interconnected shared pathways.

Inventive Principle:
Principle #1Segmentation

Solution Approach 2:

The patent applies local quality by providing dedicated heat sink portions and electrical connection pathways specific to each stacked device. Each device has its own die pad for thermal management and lead frame for electrical connection, ensuring that local requirements are met without compromising the entire stack.

Inventive Principle:
Principle #3Local quality

2Area of stationary object

If direct stacking of chips is used to improve space efficiency, then the area utilization is improved, but the cooling capability deteriorates

Engineering Contradiction:
Improvearea utilizationVSAvoidcooling capability
Core Design Contradiction:
Area of stationary objectVSTemperature

Solution Approach 1:

The patent segments the thermal management system by providing separate die pads for each stacked device. This segmentation allows each device to have independent thermal pathways to external heat sinks, preventing heat accumulation and maintaining effective cooling despite the compact vertical arrangement.

Inventive Principle:
Principle #1Segmentation

3Reliability

If an interposer is used to enable electrical interconnection between stacked devices, then the electrical connection is improved, but the package thickness and cost increase

Engineering Contradiction:
Improveelectrical connectionVSAvoidpackage thickness
Core Design Contradiction:
ReliabilityVSLength of stationary object

Solution Approach 1:

The patent extracts the electrical connection function from a separate interposer component and integrates it directly into the lead frame structure. The lead frame serves dual purposes as both mechanical support and electrical pathway, eliminating the need for an additional interposer layer and reducing overall package thickness.

Inventive Principle:
Principle #2Taking out (Extraction)

Solution Approach 2:

The lead frame is designed with multi-functionality, serving both as the mechanical support structure and as the electrical connection pathway between stacked devices. This universal component eliminates the need for separate interposer structures, reducing package complexity and thickness.

Inventive Principle:
Principle #6Universality (Multi-functionality)

4Reliability

If an interposer is used to enable electrical interconnection between stacked devices, then the electrical connection is improved, but the device complexity and cost increase

Engineering Contradiction:
Improveelectrical connectionVSAvoiddevice complexity
Core Design Contradiction:
ReliabilityVSDevice complexity

Solution Approach 1:

The lead frame is designed with multi-functionality, serving both as the mechanical support structure and as the electrical connection pathway between stacked devices. This universal component eliminates the need for separate interposer structures, reducing package complexity and thickness.

Inventive Principle:
Principle #6Universality (Multi-functionality)

Solution Approach 2:

The patent merges the electrical connection function with the mechanical support function by integrating the electrical pathways directly into the lead frame structure. This consolidation eliminates the need for separate interposer components, reducing overall device complexity and manufacturing cost.

Inventive Principle:
Principle #5Merging (Combining)

Applied Scientific Principles

This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.

Function Achieved in This Case

This approach eliminates the need for interposers, reduces package thickness and cost, and allows for efficient electrical connections between stacked devices, enhancing space efficiency and cooling capabilities.

Implementation Method 1

performing the electroless plating process so as to form an electrically conductive material only within the activated portion of the outer surface of the first mold compound

Methodology Applied
Scientific EffectElectroless plating: Electroplating

Data Source

PatentUS11296000B2Formation of conductive connection tracks in package mold body using electroless plating
Publication Date: 2022.04.05 INFINEON TECHNOLOGIES AG
  • US11296000B2 patent drawing
  • US11296000B2 patent drawing
  • US11296000B2 patent drawing

AI summary

An electronic circuit includes a first packaged semiconductor device having a first semiconductor die including a first terminal, a first electrically conductive lead that is electrically connected to the first terminal, and a first electrically insulating mold compound that encapsulates the first semiconductor die and exposes an end portion of the first lead at an outer surface of the first mold compound. A conductive track is formed in the outer surface of the first mold compound.